Fixing page table handling for non-present pages. (#617)

## Description

This change will add logic to populate the address and propagate bits
for the non-present pages.

Without this change, the issue can be seen as when a smaller page is
marked present from a big non-present page, the remainder of the
non-present pages will return `EFI_UNSUPPORTED` when using get
attributes function though protocols like CPU arch.

- [x] Impacts functionality?
- **Functionality** - Does the change ultimately impact how firmware
functions?
- Examples: Add a new library, publish a new PPI, update an algorithm,
...
- [ ] Impacts security?
- **Security** - Does the change have a direct security impact on an
application,
    flow, or firmware?
  - Examples: Crypto algorithm change, buffer overflow fix, parameter
    validation improvement, ...
- [ ] Breaking change?
- **Breaking change** - Will anyone consuming this change experience a
break
    in build or boot behavior?
- Examples: Add a new library class, move a module to a different repo,
call
    a function in a new library class in a pre-existing module, ...
- [ ] Includes tests?
  - **Tests** - Does the change include any explicit test code?
  - Examples: Unit tests, integration tests, robot tests, ...
- [ ] Includes documentation?
- **Documentation** - Does the change contain explicit documentation
additions
    outside direct code modifications (and comments)?
- Examples: Update readme file, add feature readme file, link to
documentation
    on an a separate Web page, ...

## How This Was Tested

This was tested on QEMU Q35 platform and booted to OS.

## Integration Instructions

N/A

UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c

@@ -369,6 +369,13 @@ PageTableLibMapInLevel (
       }
 
       OneOfPagingEntry.Pnle.Uint64 = 0;
+      // MU_CHANGE: Populate base address bits for non present pages
+      // TODO: Author unit test to verify the splitted pages meet expected attribute bits.
+      if ((Level != 1) && (Level != 2) && (Level != 3)) {
+        PageTableLibSetPnle (&OneOfPagingEntry.Pnle, &PleBAttribute, &AllOneMask);
+      } else {
+        PageTableLibSetPle (Level, &OneOfPagingEntry, 0, &PleBAttribute, &AllOneMask);
+      }
     } else {
       PageTableLibSetPle (Level, &OneOfPagingEntry, 0, &PleBAttribute, &AllOneMask);
     }
@@ -405,14 +412,13 @@ PageTableLibMapInLevel (
       PagingEntry = (IA32_PAGING_ENTRY *)((UINTN)Buffer + *BufferSize);
       ZeroMem (PagingEntry, SIZE_4KB);
 
-      if (ParentPagingEntry->Pce.Present) {
-        //
-        // Create 512 child-level entries that map to 2M/4K.
-        //
-        for (SubOffset = 0, Index = 0; Index < 512; Index++) {
-          PagingEntry[Index].Uint64 = OneOfPagingEntry.Uint64 + SubOffset;
-          SubOffset                += RegionLength;
-        }
+      // MU_CHANGE: Populate contents for both present and non-present pages
+      //
+      // Create 512 child-level entries that map to 2M/4K.
+      //
+      for (SubOffset = 0, Index = 0; Index < 512; Index++) {
+        PagingEntry[Index].Uint64 = OneOfPagingEntry.Uint64 + SubOffset;
+        SubOffset                += RegionLength;
       }
 
       //
@@ -496,9 +502,10 @@ PageTableLibMapInLevel (
         // e.g.: Set PDE[0-255].ReadWrite = 0
         //
         for (Index = 0; Index < 512; Index++) {
-          if (PagingEntry[Index].Pce.Present == 0) {
-            continue;
-          }
+          // MU_CHANGE: Count in the space for non-present pages as well.
+          // if (PagingEntry[Index].Pce.Present == 0) {
+          //   continue;
+          // }
 
           if (IsPle (&PagingEntry[Index], Level)) {
             PageTableLibSetPle (Level, &PagingEntry[Index], 0, &ChildAttribute, &ChildMask);