REBASE ArmPkg: ArmGicLib: Added support to send SGI to NS G1 EL1

This change extended the interface of ArmGicLib to support sending software generated interrupts to non secure group 1 at EL1. Also resolves this issue: #39. The defined macro does not exist in CLANG compiler. On the other hand, this macro is indeed for generating SGI to EL1 environment, which makes the macro definition consistent with [ARM documentation](https://developer.arm.com/documentation/ddi0601/2022-12/AArch64-Registers/ICC-SGI1R-EL1--Interrupt-Controller-Software-Generated-Interrupt-Group-1-Register?lang=en). Signed-off-by: Kun Qin <kuqin@microsoft.com>
microsoft · Dec 19, 2023 · a319b01 · a319b01
1 parent 461dcc5
commit a319b01
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diff --git a/ArmPkg/ArmPkg.ci.yaml b/ArmPkg/ArmPkg.ci.yaml
@@ -166,6 +166,7 @@
           "ipriority",
           "irouter",
           "isenabler",
+          "ishst",      # MU_CHANGE: Fix spell check error
           "istatus",
           "itargets",
           "lable",

diff --git a/ArmPkg/Drivers/ArmGic/GicV3/AArch64/ArmGicV3.S b/ArmPkg/Drivers/ArmGic/GicV3/AArch64/ArmGicV3.S
@@ -23,6 +23,7 @@
 #define ICC_IAR1_EL1            S3_0_C12_C12_0
 #define ICC_PMR_EL1             S3_0_C4_C6_0
 #define ICC_BPR1_EL1            S3_0_C12_C12_3
+#define ICC_SGI1R_EL1           S3_0_C12_C11_5  // MU_CHANGE
 
 #endif
 
@@ -55,6 +56,18 @@ ASM_FUNC(ArmGicV3SetControlSystemRegisterEnable)
 4:  isb
         ret
 
+// MU_CHANGE Starts: Add ArmGicV3SendNsG1Sgi, to allow sending SGI from one core to other cores on GICv3
+// VOID
+// ArmGicV3SendNsG1Sgi (
+//  IN UINT64          SgiVal
+//  );
+ASM_FUNC(ArmGicV3SendNsG1Sgi)
+        dsb     ishst
+        msr     ICC_SGI1R_EL1, x0
+        isb
+        ret
+// MU_CHANGE Ends
+
 //VOID
 //ArmGicV3EnableInterruptInterface (
 //  VOID

diff --git a/ArmPkg/Drivers/ArmGic/GicV3/AArch64/ArmGicV3.masm b/ArmPkg/Drivers/ArmGic/GicV3/AArch64/ArmGicV3.masm
@@ -17,6 +17,7 @@
 
     EXPORT ArmGicV3GetControlSystemRegisterEnable
     EXPORT ArmGicV3SetControlSystemRegisterEnable
+    EXPORT ArmGicV3SendNsG1Sgi  // MU_CHANGE
     EXPORT ArmGicV3EnableInterruptInterface
     EXPORT ArmGicV3DisableInterruptInterface
     EXPORT ArmGicV3EndOfInterrupt
@@ -63,6 +64,19 @@ ArmGicV3SetControlSystemRegisterEnable PROC
         ret
 ArmGicV3SetControlSystemRegisterEnable ENDP
 
+// MU_CHANGE Starts: Add ArmGicV3SendNsG1Sgi, to allow sending SGI from one core to other cores on GICv3
+// VOID
+// ArmGicV3SendNsG1Sgi (
+//  IN UINT64          SgiVal
+//  );
+ArmGicV3SendNsG1Sgi PROC
+        dsb     ishst
+        msr     ICC_SGI1R, x0
+        isb
+        ret
+ArmGicV3SendNsG1Sgi ENDP
+// MU_CHANGE Ends
+
 //VOID
 //ArmGicV3EnableInterruptInterface (
 //  VOID

diff --git a/ArmPkg/Drivers/ArmGic/GicV3/Arm/ArmGicV3.S b/ArmPkg/Drivers/ArmGic/GicV3/Arm/ArmGicV3.S
@@ -29,6 +29,18 @@ ASM_FUNC(ArmGicV3SetControlSystemRegisterEnable)
         isb
         bx      lr
 
+// MU_CHANGE Starts: Add ArmGicV3SendNsG1Sgi, to allow sending SGI from one core to other cores on GICv3
+// VOID
+// ArmGicV3SendNsG1Sgi (
+//  IN UINT64          SgiVal
+//  );
+ASM_FUNC(ArmGicV3SendNsG1Sgi)
+        dsb     ishst
+        mcrr    p15, 0, r0, r1, c12 // ICC_SGI1R_EL1
+        isb
+        bx      lr
+// MU_CHANGE Ends
+
 //VOID
 //ArmGicV3EnableInterruptInterface (
 //  VOID

diff --git a/ArmPkg/Include/Library/ArmGicLib.h b/ArmPkg/Include/Library/ArmGicLib.h
@@ -336,4 +336,12 @@ ArmGicV3SetPriorityMask (
   IN UINTN  Priority
   );
 
+// MU_CHANGE Starts: Add ArmGicV3SendNsG1Sgi, to allow sending SGI from one core to other cores on GICv3
+VOID
+ArmGicV3SendNsG1Sgi (
+  IN UINT64  SgiVal
+  );
+
+// MU_CHANGE Ends
+
 #endif // ARMGIC_H_