Project Tang enables a fully open-source flow for Anlogic FPGAs using Yosys for Verilog synthesis and nextpnr for place and route. Project Tang itself provides the device database and tools for bitstream creation.
This repository contains both tools and scripts which allow you to document the bit-stream format of Anlogic series FPGAs.
Translation of offical documents can be found here.
Take latest TD distribution from Sipeed.com Point out TD_HOME to your TangDinasty installation and set environment.
export TD_HOME=/opt/TD
source environment.sh
To create chip database run:
python3 create_database.py
In order to get HTML representation of tilegrid data after run:
python3 html_all.py
Miscellaneous tools for exploring the database and experimenting with bitstreams.
Python libraries used for fuzzers and other purposes
Running the all fuzzers in order will produce a database which documents the bitstream format in the database directory.
Code is heavily based on prjtrellis. Special thanks goes to @gatecat
There are a couple of guidelines when contributing to Project Tang which are listed here.
All contributions should be sent as GitHub Pull requests.
All code in the Project Tang repository is licensed under the very permissive
ISC Licence. A copy can be found in the COPYING file.
All new contributions must also be released under this license.
By contributing you agree to the code of conduct. We follow the open source best practice of using the Contributor Covenant for our Code of Conduct.
