Analog-Design-of-Bootstrapped-Switch

This project shows how to design a clock bootstrapped circuit to improve the nonlinearity of the switch used in Track & Hold circuit. A comparison is done between several topologies, showing the ENOB, SNR, & SFDR achieved in each case.

A) S/H Using Ideal Switch

B) S/H Using NMOS or PMOS

C) S/H Using CMOS TG

D) S/H Using Bootstrapped Circuit with ideal switches

E) S/H Using Bootstrapped Circuit (Topology 1)

F) S/H Using Bootstrapped Circuit (Topology 2)

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Results

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References:

My project on google drive:
https://drive.google.com/drive/folders/1W9ip4MpMZNf3IQsoFQkhgg6QaUya4Yp4
EE288 Lecture Notes:
https://drive.google.com/drive/folders/12Qqfw_TX1i7dvVVYXksaSdHV4gth1OD5
Videos on how to create VerilogA blocks for ADCs: https://drive.google.com/drive/folders/1GAobRzzFTkD6ywqSdDJUsO5g2C06hh_i
https://www.youtube.com/channel/UC7jwESeWKLcRbtxHwFS3A7Q/videos