This work is aimed at design of a 10bit potentiometric DAC with 3.3V analog output volatge and 1.8V digital inputs with a single external reference voltage source. The DAC is designed using multiple stages for better performance and less area requirements compared to a single stage DAC.
The required design specifications can be found here
Modern electronic systems dominate due to the evolution in digital technology. However the outside world remains analog in nature. DACs form an important link to connect between the digital systems to the analog world.
Binary weighted DAC, R-2R DAC, current steering DAC are some of the DAC architectures used in various applications. However this work is done to develop a potentiometric DAC.
| Name | No. | I/O | Description |
|---|---|---|---|
| D[0:9] | 1-10 | I | Digital inputs |
| EN | 11 | I | Enable pin |
| VDD | 12 | I | Digital power supply(1.8) |
| VSS | 13 | I | Digital ground |
| OUT | 14 | O | DAC analog voltage output |
| VDDA | 1 | I | Analog voltage supply (3.3) |
| VSSA | 16 | I | Analog ground |
| VREFH | 17 | I | Reference voltage high for DAC |
| VREFL | 18 | I | Reference voltage low for DAC |
| Parameter | Description | min | typ | max | Unit | Condition |
|---|---|---|---|---|---|---|
| RL | Load resistance | 50 | Mohm | T=-40 to 85C | ||
| CL | Load capacitance | 1 | pF | T=-40 to 85C | ||
| VDDA | Analog supply voltage | 3.3 | V | T=-40 to 85C | ||
| VDD | Digital supply voltage | 1.8 | V | T=-40 to 85C | ||
| VREFH | Reference Voltage high | 3.3 | V | T=-40 to 85C | ||
| VREFL | Reference Voltage low | 0 | V | T=-40 to 85C | ||
| RES | Resolution | 10 | bits | On all above condition for "typ" (T=27C) | ||
| INL | Integral non-linearity | -0.921 to +2.374 | LSB | On all above condition for "typ" (T=27C) | ||
| DNL | Differential non-linearity | -0.247 to +1.44 | LSB | On all above condition for "typ" (T=27C) | ||
| TCONV | Conversion time | 9.99 | us | T=27C | ||
| IDDA | Analog supply current | 100 | mA | T=27C, Data change=16K samples/sec | ||
| IDD | Digital supply current | 114.25 | mA | T=27C, Data change=16K samples/sec |
The 10bit DAC is designed in three stages to save area and reduce the runtime. The prelayout and postlayout simulations ran within 3 minutes. It requires a total of 44 resistors and 79 switch pairs.
- The development of an area-efficient multiple-output voltage selector starts from a 5-b tree-type two-voltage selector. This circuit requires two sets of 5-b tree-type decoders, arranged with a 1-b offset, in order to select two adjacent voltages from a resistor string.
- One set outputs VH and the other set outputs VL. A total of 124 switches are required. The two-voltage selector chooses two adjacent voltages from the reference voltages of a global resistor string according to the higher digital bits (MSB bits b9 to b5) and connects them to the succeeding DAC stages.
- The second stage is again a 3-b tree-type two-voltage selector which outputs VH and VL based on subsequent LSB bits from b4 to b2.
- The third stage is a 2 bit DAC which subsequently divides the voltage between these two voltage levels based on lower 2 digital bits b1 and b0.
Note: The accuracy of the conversion can be improved by adjusting the number of stages and granularity of different stages.
The circuit is an extended version of stage 2 circuit with 5-bit selector switches. It is created using the subcircuits of stage 2 circuit and switch pair circuit.
The complete circuit diagram can be downloaded using this link 10bitDAC_Circuit.pdf
Note- While integrating the different stages, the resistance values have been changed appropriately.
The differential nonlinearity (DNL) is the difference between the measured and ideal 1LSB amplitude change of any two adjacent codes. Using the values noted earlier and the formula given below, we can find all the DNL values. These vaues are uploaded in the repository with the name DNL_INL_calculations.
DNL(LSB)= (Actual height- Ideal height)/1LSB
The relative accuracy or integral nonlinearity (INL) is the maximum deviation of the output from the line between zero and full scale excluding the effects of zero code and full-scale errors. The calculated INL values are uploaded in the repository in the file with the name DNL_INL_calculations.
INL(LSB)= (Actual Vout-Reference Vout)/1LSB
| Parameter | Pre-layout | Post-layout |
|---|---|---|
| DNL(LSB) | -1.0 to +1.7 | -0.247 to +1.44 |
| INL (LSB) | -2.0 to +2.654 | -0.921 to +2.374 |
The obtained ouptput values are tabulated and given in the folder 'caluclations and plots' and can be plotted using excel or SciDAVis plotting software.
Note- The input code ranges from 0 to 1023. The Full Scale output voltage, VFS =3.292069V
The design is done using opensource EDA tools such as eSim for the prelayout simulatioms and MAGIC for the layout and postlayout simulations. eSim is a free and open source EDA tool for circuit design, simulation, analysis and PCB design. It is an integrated tool built using open source software such as KiCad, Ngspice and GHDL. Magic is an opensource VLSI layout tool.
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Go to the link https://github.com/FOSSEE/eSim/releases/tag/v1.1.3 and download eSim-1.1.3 for Ubuntu.
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After downloading eSim, extract it using:
$ unzip eSim-1.1.3.zip -
Now change directories in to the top-level source directory (where this INSTALL file can be found).
To install eSim and other dependecies run the following command.
$ ./install-eSim.sh --installAbove script will install eSim along with dependencies.
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To Run eSim
Double click eSim desktop icon. To open through terminal, use the command
$ esim
Refer Spoken Tutorial (https://spoken-tutorial.org/tutorial-search/?search_foss=eSim) for eSim installation on Linux and MS Windows.
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Download the https://drive.google.com/file/d/1F0y1xuYWIgeYEpzKnGlaCQH3urdSFc4E/view file
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Copy paste the below commands one after another
$ cd Downloads/ $ chmod +x magic.sh $ ./magic.sh -
Magic tool will be opened with minimum technology file by default. Follow below steps to open magic with osu180nm tech file.
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Download the SCN6M_SUBM.10.tech from the uploaded files. Copy and paste the entire content in Text Editor and save it as osu180nm.tech.
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Open the Terminal and copy, paste the commands mentioned below.
$ sudo cp osu180nm.tech /usr/local/lib/magic/sys/ $ cd /usr/local/lib/magic/sys/ $ ls $ cd $ clear
You have successfully added osu180nm.tech file!
Just open the terminal and type magic -T osu180nm.tech filename.mag to begin layout.
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To clone the Repository and download the Netlist files for Simulation, enter the following commands in your terminal.
$ sudo apt install -y git $ git clone https://https://github.com/neethujohny/avsddac_3v3 $ cd avsddac_3v3/Prelayout_Netlist -
To run the Transient Analysis , enter the following command
$ ngspice Vh_Vl_cascaded.cir.out $ plot out_10bitdac
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To clone the Repository and download the Netlist files for Simulation, enter the following commands in your terminal.
$ sudo apt install -y git $ git clone https://https://github.com/neethujohny/avsddac_3v3 $ cd avsddac_3v3/PostLayout_magic and spice files -
To run the Transient Analysis , enter the following command
$ ngspice 10bit_dac.spice
Note: For the stage wise simulation outputs, please refer post layout simulation file uploaded above.
- Build a more compact layout to meet the area specifications.
- Improve the DNL and INL by increasing the resolution of different stages.
- Improve the conversion rate to meet the specification.
- Modify the design (Resistor chain) to meet the power consumption requirements.
- Build the layout of a capacitor (the necessary layers are not included in the osu). In this project the capacitor is manually added in the extracted netlist.
Neethu Johny, Research Scholar, B.M.S College of Engineering, Bangalore
- https://patents.google.com/patent/US6249239
- Chih-Wen Lu, Member, IEEE, Ching-Min Hsiao, and Ping-Yeh Yin, A 10-b Two-Stage DAC with an Area-Efficient Multiple-Output Voltage Selector and a Linearity-Enhanced DAC- Embedded Op-Amp for LCD Column Driver ICs, IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 48, NO. 6, JUNE 2013
- Yoo-Chang Sung, Oh-Kyong Kwon,Jong-Kee Kim ,10-bit source driver with resistor-resistor-string digital-to-analog converter,Journal of the SID 14/4, 2006
- https://github.com/ankursah5/avsdbgp_3v3
- https://github.com/VSD-DACteam/avsddac_3v3
- https://github.com/FOSSEE/eSim
- http://opencircuitdesign.com/magic
Kunal Ghosh, Director, VSD Corp. Pvt. Ltd.
Philipp Gühring, Software Architect, LibreSilicon Assocation
FOSSEE Team, IIT Bombay
R. Timothy Edwards, Open Circuit Design
Neethu Johny, B.M.S College of Engineering, Bangalore - neethujohny123@gmail.com
Kunal Ghosh, Co-founder, VSD Corp. Pvt. Ltd. - kunalghosh@gmail.com
Philipp Gühring, Software Architect, LibreSilicon Assocation - pg@futureware.at