Pinned Loading
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Risc-v-chip8
Risc-v-chip8 PublicThis is my created Risc-v cpu core on verilog and my created chip8 emulator ,which is running on it
C 6
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wltoys-v202-protocol
wltoys-v202-protocol PublicThis project is full functional implementation of wltoys v202 protocol,specified for rc cars A959, A969, A979 in micropython or esp32 idf with nrf24l01 module
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fpga_mandelbrot_fractal
fpga_mandelbrot_fractal PublicMandelbrot fractal generator in verilog
Verilog 2
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