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Fix build failed
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@luyahan
luyahan committed Jun 11, 2021
1 parent ac9cf34 commit 8d10f25
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Showing 4 changed files with 225 additions and 53 deletions.
181 changes: 171 additions & 10 deletions deps/v8/src/builtins/riscv64/builtins-riscv64.cc
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Original file line number Diff line number Diff line change
Expand Up @@ -1542,22 +1542,32 @@ void Builtins::Generate_NotifyDeoptimized(MacroAssembler* masm) {
__ Ret();
}

void Builtins::Generate_InterpreterOnStackReplacement(MacroAssembler* masm) {
namespace {

void Generate_OSREntry(MacroAssembler* masm, Register entry_address,
Operand offset = Operand(int64_t(0))) {
__ Add64(ra, entry_address, offset);
// And "return" to the OSR entry point of the function.
__ Ret();
}

void OnStackReplacement(MacroAssembler* masm, bool is_interpreter) {
{
FrameScope scope(masm, StackFrame::INTERNAL);
__ CallRuntime(Runtime::kCompileForOnStackReplacement);
}

// If the code object is null, just return to the caller.
__ Ret(eq, a0, Operand(Smi::zero()));

// Drop the handler frame that is be sitting on top of the actual
// JavaScript frame. This is the case then OSR is triggered from bytecode.
__ LeaveFrame(StackFrame::STUB);

if (is_interpreter) {
// Drop the handler frame that is be sitting on top of the actual
// JavaScript frame. This is the case then OSR is triggered from bytecode.
__ LeaveFrame(StackFrame::STUB);
}
// Load deoptimization data from the code object.
// <deopt_data> = <code>[#deoptimization_data_offset]
__ Ld(a1, MemOperand(a0, Code::kDeoptimizationDataOffset - kHeapObjectTag));
__ Ld(
a1, MemOperand(a0, Code::kDeoptimizationDataOffset - kHeapObjectTag));

// Load the OSR entrypoint offset from the deoptimization data.
// <osr_offset> = <deopt_data>[#header_size + #osr_pc_offset]
Expand All @@ -1568,11 +1578,16 @@ void Builtins::Generate_InterpreterOnStackReplacement(MacroAssembler* masm) {
// Compute the target address = code_obj + header_size + osr_offset
// <entry_addr> = <code_obj> + #header_size + <osr_offset>
__ Add64(a0, a0, a1);
__ Add64(ra, a0, Code::kHeaderSize - kHeapObjectTag);
// And "return" to the OSR entry point of the function.
__ Ret();
Generate_OSREntry(masm, a0, Operand(Code::kHeaderSize - kHeapObjectTag));
}
} // namespace

void Builtins::Generate_InterpreterOnStackReplacement(MacroAssembler* masm) {
return OnStackReplacement(masm, true);
}



// static
void Builtins::Generate_FunctionPrototypeApply(MacroAssembler* masm) {
// ----------- S t a t e -------------
Expand Down Expand Up @@ -3252,6 +3267,152 @@ void Builtins::Generate_DeoptimizationEntry_Lazy(MacroAssembler* masm) {
Generate_DeoptimizationEntry(masm, DeoptimizeKind::kLazy);
}

namespace {

// Converts an interpreter frame into a baseline frame and continues execution
// in baseline code (baseline code has to exist on the shared function info),
// either at the start or the end of the current bytecode.
void Generate_BaselineEntry(MacroAssembler* masm, bool next_bytecode,
bool is_osr = false) {
__ Push(zero_reg, kInterpreterAccumulatorRegister);
Label start;
__ bind(&start);

// Get function from the frame.
Register closure = a1;
__ Ld(closure, MemOperand(fp, StandardFrameConstants::kFunctionOffset));

// Replace BytecodeOffset with the feedback vector.
Register feedback_vector = a2;
__ Ld(
feedback_vector,
FieldMemOperand(closure, JSFunction::kFeedbackCellOffset));
__ Ld(
feedback_vector, FieldMemOperand(feedback_vector, Cell::kValueOffset));
Label install_baseline_code;
// Check if feedback vector is valid. If not, call prepare for baseline to
// allocate it.
UseScratchRegisterScope temps(masm);
Register type = temps.Acquire();
__ GetObjectType(feedback_vector, type, type);
__ Branch(&install_baseline_code, eq, type, Operand(FEEDBACK_VECTOR_TYPE));
// Save BytecodeOffset from the stack frame.
__ SmiUntag(kInterpreterBytecodeOffsetRegister,
MemOperand(fp, InterpreterFrameConstants::kBytecodeOffsetFromFp));
// Replace BytecodeOffset with the feedback vector.
__ Sd(feedback_vector,
MemOperand(fp, InterpreterFrameConstants::kBytecodeOffsetFromFp));
feedback_vector = no_reg;

// Get the Code object from the shared function info.
Register code_obj = type;
__ Ld(
code_obj,
FieldMemOperand(closure, JSFunction::kSharedFunctionInfoOffset));
__ Ld(
code_obj,
FieldMemOperand(code_obj, SharedFunctionInfo::kFunctionDataOffset));
__ Ld(
code_obj, FieldMemOperand(code_obj, BaselineData::kBaselineCodeOffset));

// Compute baseline pc for bytecode offset.
__ Push(zero_reg, kInterpreterAccumulatorRegister);
ExternalReference get_baseline_pc_extref;
if (next_bytecode || is_osr) {
get_baseline_pc_extref =
ExternalReference::baseline_pc_for_next_executed_bytecode();
} else {
get_baseline_pc_extref =
ExternalReference::baseline_pc_for_bytecode_offset();
}

Register get_baseline_pc = a3;
__ li(get_baseline_pc, get_baseline_pc_extref);

// If the code deoptimizes during the implicit function entry stack interrupt
// check, it will have a bailout ID of kFunctionEntryBytecodeOffset, which is
// not a valid bytecode offset.
// TODO(pthier): Investigate if it is feasible to handle this special case
// in TurboFan instead of here.
Label valid_bytecode_offset, function_entry_bytecode;
if (!is_osr) {
__ Branch(&function_entry_bytecode, eq, kInterpreterBytecodeOffsetRegister,
Operand(BytecodeArray::kHeaderSize - kHeapObjectTag +
kFunctionEntryBytecodeOffset));
}

__ Sub64(kInterpreterBytecodeOffsetRegister,
kInterpreterBytecodeOffsetRegister,
(BytecodeArray::kHeaderSize - kHeapObjectTag));

__ bind(&valid_bytecode_offset);
// Get bytecode array from the stack frame.
__ Ld(kInterpreterBytecodeArrayRegister,
MemOperand(fp, InterpreterFrameConstants::kBytecodeArrayFromFp));
{
Register arg_reg_1 = a0;
Register arg_reg_2 = a1;
Register arg_reg_3 = a2;
__ Move(arg_reg_1, code_obj);
__ Move(arg_reg_2, kInterpreterBytecodeOffsetRegister);
__ Move(arg_reg_3, kInterpreterBytecodeArrayRegister);
FrameScope scope(masm, StackFrame::INTERNAL);
__ CallCFunction(get_baseline_pc, 3, 0);
}
__ Add64(code_obj, code_obj, kReturnRegister0);
__ Pop(kInterpreterAccumulatorRegister, zero_reg);

if (is_osr) {
// Reset the OSR loop nesting depth to disarm back edges.
// TODO(pthier): Separate baseline Sparkplug from TF arming and don't disarm
// Sparkplug here.
__ Sd(zero_reg, FieldMemOperand(kInterpreterBytecodeArrayRegister,
BytecodeArray::kOsrNestingLevelOffset));
Generate_OSREntry(masm, code_obj,
Operand(Code::kHeaderSize - kHeapObjectTag));
} else {
__ Add64(code_obj, code_obj, Code::kHeaderSize - kHeapObjectTag);
__ Jump(code_obj);
}
__ Trap(); // Unreachable.

if (!is_osr) {
__ bind(&function_entry_bytecode);
// If the bytecode offset is kFunctionEntryOffset, get the start address of
// the first bytecode.
__ li(kInterpreterBytecodeOffsetRegister, Operand(int64_t(0)));
if (next_bytecode) {
__ li(get_baseline_pc,
ExternalReference::baseline_pc_for_bytecode_offset());
}
__ Branch(&valid_bytecode_offset);
}

__ bind(&install_baseline_code);
{
FrameScope scope(masm, StackFrame::INTERNAL);
__ Push(closure);
__ CallRuntime(Runtime::kInstallBaselineCode, 1);
}
// Retry from the start after installing baseline code.
__ Branch(&start);
}

} // namespace

void Builtins::Generate_BaselineEnterAtBytecode(MacroAssembler* masm) {
Generate_BaselineEntry(masm, false);
}

void Builtins::Generate_BaselineEnterAtNextBytecode(MacroAssembler* masm) {
Generate_BaselineEntry(masm, true);
}

void Builtins::Generate_InterpreterOnStackReplacement_ToBaseline(
MacroAssembler* masm) {
Generate_BaselineEntry(masm, false, true);
}

void Builtins::Generate_DynamicCheckMapsTrampoline(MacroAssembler* masm) {
FrameScope scope(masm, StackFrame::MANUAL);
__ EnterFrame(StackFrame::INTERNAL);
Expand Down
84 changes: 42 additions & 42 deletions deps/v8/src/codegen/riscv64/constants-riscv64.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -215,54 +215,54 @@ const int kRvcFunct6Shift = 10;
const int kRvcFunct6Bits = 6;

// RISCV Instruction bit masks
const int kBaseOpcodeMask = ((1 << kBaseOpcodeBits) - 1) << kBaseOpcodeShift;
const int kFunct3Mask = ((1 << kFunct3Bits) - 1) << kFunct3Shift;
const int kFunct5Mask = ((1 << kFunct5Bits) - 1) << kFunct5Shift;
const int kFunct7Mask = ((1 << kFunct7Bits) - 1) << kFunct7Shift;
const int kFunct2Mask = 0b11 << kFunct7Shift;
const int kRTypeMask = kBaseOpcodeMask | kFunct3Mask | kFunct7Mask;
const int kRATypeMask = kBaseOpcodeMask | kFunct3Mask | kFunct5Mask;
const int kRFPTypeMask = kBaseOpcodeMask | kFunct7Mask;
const int kR4TypeMask = kBaseOpcodeMask | kFunct3Mask | kFunct2Mask;
const int kITypeMask = kBaseOpcodeMask | kFunct3Mask;
const int kSTypeMask = kBaseOpcodeMask | kFunct3Mask;
const int kBTypeMask = kBaseOpcodeMask | kFunct3Mask;
const int kUTypeMask = kBaseOpcodeMask;
const int kJTypeMask = kBaseOpcodeMask;
const int kRs1FieldMask = ((1 << kRs1Bits) - 1) << kRs1Shift;
const int kRs2FieldMask = ((1 << kRs2Bits) - 1) << kRs2Shift;
const int kRs3FieldMask = ((1 << kRs3Bits) - 1) << kRs3Shift;
const int kRdFieldMask = ((1 << kRdBits) - 1) << kRdShift;
const int kBImm12Mask = kFunct7Mask | kRdFieldMask;
const int kImm20Mask = ((1 << kImm20Bits) - 1) << kImm20Shift;
const int kImm12Mask = ((1 << kImm12Bits) - 1) << kImm12Shift;
const int kImm11Mask = ((1 << kImm11Bits) - 1) << kImm11Shift;
const int kImm31_12Mask = ((1 << 20) - 1) << 12;
const int kImm19_0Mask = ((1 << 20) - 1);
const int kRvcOpcodeMask =
const uint32_t kBaseOpcodeMask = ((1 << kBaseOpcodeBits) - 1) << kBaseOpcodeShift;
const uint32_t kFunct3Mask = ((1 << kFunct3Bits) - 1) << kFunct3Shift;
const uint32_t kFunct5Mask = ((1 << kFunct5Bits) - 1) << kFunct5Shift;
const uint32_t kFunct7Mask = ((1 << kFunct7Bits) - 1) << kFunct7Shift;
const uint32_t kFunct2Mask = 0b11 << kFunct7Shift;
const uint32_t kRTypeMask = kBaseOpcodeMask | kFunct3Mask | kFunct7Mask;
const uint32_t kRATypeMask = kBaseOpcodeMask | kFunct3Mask | kFunct5Mask;
const uint32_t kRFPTypeMask = kBaseOpcodeMask | kFunct7Mask;
const uint32_t kR4TypeMask = kBaseOpcodeMask | kFunct3Mask | kFunct2Mask;
const uint32_t kITypeMask = kBaseOpcodeMask | kFunct3Mask;
const uint32_t kSTypeMask = kBaseOpcodeMask | kFunct3Mask;
const uint32_t kBTypeMask = kBaseOpcodeMask | kFunct3Mask;
const uint32_t kUTypeMask = kBaseOpcodeMask;
const uint32_t kJTypeMask = kBaseOpcodeMask;
const uint32_t kRs1FieldMask = ((1 << kRs1Bits) - 1) << kRs1Shift;
const uint32_t kRs2FieldMask = ((1 << kRs2Bits) - 1) << kRs2Shift;
const uint32_t kRs3FieldMask = ((1 << kRs3Bits) - 1) << kRs3Shift;
const uint32_t kRdFieldMask = ((1 << kRdBits) - 1) << kRdShift;
const uint32_t kBImm12Mask = kFunct7Mask | kRdFieldMask;
const uint32_t kImm20Mask = ((1 << kImm20Bits) - 1) << kImm20Shift;
const uint32_t kImm12Mask = ((1 << kImm12Bits) - 1) << kImm12Shift;
const uint32_t kImm11Mask = ((1 << kImm11Bits) - 1) << kImm11Shift;
const uint32_t kImm31_12Mask = ((1 << 20) - 1) << 12;
const uint32_t kImm19_0Mask = ((1 << 20) - 1);
const uint32_t kRvcOpcodeMask =
0b11 | (((1 << kRvcFunct3Bits) - 1) << kRvcFunct3Shift);
const int kRvcFunct3Mask = (((1 << kRvcFunct3Bits) - 1) << kRvcFunct3Shift);
const int kRvcFunct4Mask = (((1 << kRvcFunct4Bits) - 1) << kRvcFunct4Shift);
const int kRvcFunct6Mask = (((1 << kRvcFunct6Bits) - 1) << kRvcFunct6Shift);
const int kRvcFunct2Mask = (((1 << kRvcFunct2Bits) - 1) << kRvcFunct2Shift);
const int kCRTypeMask = kRvcOpcodeMask | kRvcFunct4Mask;
const int kCSTypeMask = kRvcOpcodeMask | kRvcFunct6Mask;
const int kCATypeMask = kRvcOpcodeMask | kRvcFunct6Mask | kRvcFunct2Mask;
const uint32_t kRvcFunct3Mask = (((1 << kRvcFunct3Bits) - 1) << kRvcFunct3Shift);
const uint32_t kRvcFunct4Mask = (((1 << kRvcFunct4Bits) - 1) << kRvcFunct4Shift);
const uint32_t kRvcFunct6Mask = (((1 << kRvcFunct6Bits) - 1) << kRvcFunct6Shift);
const uint32_t kRvcFunct2Mask = (((1 << kRvcFunct2Bits) - 1) << kRvcFunct2Shift);
const uint32_t kCRTypeMask = kRvcOpcodeMask | kRvcFunct4Mask;
const uint32_t kCSTypeMask = kRvcOpcodeMask | kRvcFunct6Mask;
const uint32_t kCATypeMask = kRvcOpcodeMask | kRvcFunct6Mask | kRvcFunct2Mask;

// RISCV CSR related bit mask and shift
const int kFcsrFlagsBits = 5;
const int kFcsrFlagsMask = (1 << kFcsrFlagsBits) - 1;
const int kFcsrFrmBits = 3;
const int kFcsrFrmShift = kFcsrFlagsBits;
const int kFcsrFrmMask = ((1 << kFcsrFrmBits) - 1) << kFcsrFrmShift;
const int kFcsrBits = kFcsrFlagsBits + kFcsrFrmBits;
const int kFcsrMask = kFcsrFlagsMask | kFcsrFrmMask;
const uint32_t kFcsrFlagsBits = 5;
const uint32_t kFcsrFlagsMask = (1 << kFcsrFlagsBits) - 1;
const uint32_t kFcsrFrmBits = 3;
const uint32_t kFcsrFrmShift = kFcsrFlagsBits;
const uint32_t kFcsrFrmMask = ((1 << kFcsrFrmBits) - 1) << kFcsrFrmShift;
const uint32_t kFcsrBits = kFcsrFlagsBits + kFcsrFrmBits;
const uint32_t kFcsrMask = kFcsrFlagsMask | kFcsrFrmMask;

// Original MIPS constants
// TODO(RISCV): to be cleaned up
const int kImm16Shift = 0;
const int kImm16Bits = 16;
const int kImm16Mask = ((1 << kImm16Bits) - 1) << kImm16Shift;
const uint32_t kImm16Shift = 0;
const uint32_t kImm16Bits = 16;
const uint32_t kImm16Mask = ((1 << kImm16Bits) - 1) << kImm16Shift;
// end of TODO(RISCV): to be cleaned up

// ----- RISCV Base Opcodes
Expand Down
7 changes: 6 additions & 1 deletion deps/v8/src/compiler/backend/riscv64/code-generator-riscv64.cc
View file
Original file line number Diff line number Diff line change
Expand Up @@ -508,6 +508,11 @@ void AdjustStackPointerForTailCall(TurboAssembler* tasm,

} // namespace

void CodeGenerator::AssembleArchSelect(Instruction* instr,
FlagsCondition condition) {
UNIMPLEMENTED();
}

void CodeGenerator::AssembleTailCallBeforeGap(Instruction* instr,
int first_unused_slot_offset) {
AdjustStackPointerForTailCall(tasm(), frame_access_state(),
Expand Down Expand Up @@ -2578,7 +2583,7 @@ void CodeGenerator::AssembleMove(InstructionOperand* source,
}
case Constant::kCompressedHeapObject:
UNREACHABLE();
case Constant::kRpoNumber:
case Constant::kRpoNumber:
UNREACHABLE(); // TODO(titzer): loading RPO numbers
break;
}
Expand Down
6 changes: 6 additions & 0 deletions deps/v8/src/wasm/baseline/riscv64/liftoff-assembler-riscv64.h
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Original file line number Diff line number Diff line change
Expand Up @@ -414,6 +414,12 @@ void LiftoffAssembler::LoadTaggedPointer(Register dst, Register src_addr,
Ld(dst, src_op);
}

void LiftoffAssembler::LoadFullPointer(Register dst, Register src_addr,
int32_t offset_imm) {
MemOperand src_op = liftoff::GetMemOp(this, src_addr, no_reg, offset_imm);
Ld(dst, src_op);
}

void LiftoffAssembler::StoreTaggedPointer(Register dst_addr,
Register offset_reg,
int32_t offset_imm,
Expand Down

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