PSoC 5 support

csrc/u8g.h

@@ -415,6 +415,7 @@ extern u8g_dev_t u8g_dev_ssd1325_nhd27oled_bw_hw_spi;
 extern u8g_dev_t u8g_dev_ssd1325_nhd27oled_bw_parallel;
 extern u8g_dev_t u8g_dev_ssd1325_nhd27oled_gr_sw_spi;
 extern u8g_dev_t u8g_dev_ssd1325_nhd27oled_gr_hw_spi;
+extern u8g_dev_t u8g_dev_ssd1325_nhd27oled_gr_parallel;
 
 extern u8g_dev_t u8g_dev_ssd1325_nhd27oled_2x_bw_sw_spi;
 extern u8g_dev_t u8g_dev_ssd1325_nhd27oled_2x_bw_hw_spi;
@@ -703,6 +704,8 @@ uint8_t u8g_com_msp430_hw_spi_fn(u8g_t *u8g, uint8_t msg, uint8_t arg_val, void
 uint8_t u8g_com_raspberrypi_hw_spi_fn(u8g_t *u8g, uint8_t msg, uint8_t arg_val, void *arg_ptr);                /* u8g_com_rasperrypi_hw_spi.c */
 uint8_t u8g_com_raspberrypi_ssd_i2c_fn(u8g_t *u8g, uint8_t msg, uint8_t arg_val, void *arg_ptr);		/* u8g_com_raspberrypi_ssd_i2c.c */
 
+uint8_t u8g_com_psoc5_ssd_hw_spi_fn(u8g_t *u8g, uint8_t msg, uint8_t arg_val, void *arg_ptr);   /* u8g_com_psoc5_ssd_hw_spi.c */
+uint8_t u8g_com_psoc5_ssd_hw_parallel_fn(u8g_t *u8g, uint8_t msg, uint8_t arg_val, void *arg_ptr);   /* u8g_com_psoc5_ssd_hw_parallel.c */
 
 /* 
   Translation of system specific com drives to generic com names
@@ -856,6 +859,10 @@ defined(__18CXX) || defined(__PIC32MX)
 #define U8G_COM_SSD_I2C u8g_com_raspberrypi_ssd_i2c_fn
 #endif
 #endif
+#if defined(U8G_CYPRESS_PSOC5)
+#define U8G_COM_HW_SPI u8g_com_psoc5_ssd_hw_spi_fn
+#define U8G_COM_FAST_PARALLEL u8g_com_psoc5_ssd_hw_parallel_fn
+#endif
 
 #ifndef U8G_COM_SSD_I2C
 #define U8G_COM_SSD_I2C u8g_com_null_fn

csrc/u8g_com_psoc5_ssd_hw_parallel.c

@@ -0,0 +1,107 @@
+/*
+
+  u8g_com_psoc5_ssd_hw_parallel.c
+
+  com interface for Cypress PSoC5 and the SSDxxxx chip variant
+  I2C protocol
+
+  Universal 8bit Graphics Library
+
+  Copyright (c) 2015, olikraus@gmail.com, schmidt.ronny@gmail.com
+  All rights reserved.
+
+  Redistribution and use in source and binary forms, with or without modification, 
+  are permitted provided that the following conditions are met:
+
+  * Redistributions of source code must retain the above copyright notice, this list 
+    of conditions and the following disclaimer.
+
+  * Redistributions in binary form must reproduce the above copyright notice, this 
+    list of conditions and the following disclaimer in the documentation and/or other 
+    materials provided with the distribution.
+
+  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND 
+  CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, 
+  INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 
+  DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR 
+  CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
+  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 
+  NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 
+  LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 
+  CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 
+  STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 
+  ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.  
+
+
+*/
+
+#include "u8g.h"
+
+#if defined(U8G_CYPRESS_PSOC5)
+
+#include <project.h>   
+
+static uint8 dc = 0; // need to store whether next write is data or command
+
+uint8_t u8g_com_psoc5_ssd_hw_parallel_fn(u8g_t *u8g, uint8_t msg, uint8_t arg_val, void *arg_ptr)
+{
+  switch(msg)
+  {
+    case U8G_COM_MSG_STOP:
+      // stop the device
+      GraphicLCDIntf_Stop();
+      break;
+
+    case U8G_COM_MSG_INIT:
+  		// init hardware interfaces, timers, gpios, ...
+      GraphicLCDIntf_Init();
+      break;
+
+    case U8G_COM_MSG_ADDRESS:                     
+      // switch from cmd (arg_val = 0) to data mode (arg_val = 1) or vice versa
+      dc = arg_val;
+      break;
+
+    case U8G_COM_MSG_CHIP_SELECT:
+		  /* done by the hardware */
+      break;
+
+    case U8G_COM_MSG_RESET:
+      // toggle the reset pin of the display by value in arg_val
+      nRES_Write(0);
+      u8g_10MicroDelay();
+      nRES_Write(1);
+      break;
+
+    case U8G_COM_MSG_WRITE_BYTE:
+      // write byte to the device
+		  GraphicLCDIntf_Write8(dc, arg_val);
+      break;
+
+    case U8G_COM_MSG_WRITE_SEQ:
+    case U8G_COM_MSG_WRITE_SEQ_P:
+      {
+        // write a sequence of bytes to the device
+        register uint8_t *ptr = arg_ptr;
+        while (arg_val-- > 0)
+        {
+          GraphicLCDIntf_Write8(dc, *ptr++);
+        }
+      }
+      break;
+
+
+  }
+  return 1;
+}
+
+#else
+
+uint8_t u8g_com_psoc5_ssd_hw_spi_fn(u8g_t *u8g, uint8_t msg, uint8_t arg_val, void *arg_ptr)
+{
+  return 1;
+}
+
+#endif

csrc/u8g_delay.c

@@ -71,6 +71,8 @@
 #  define USE_AVR_DELAY
 #elif defined(__18CXX)
 #  define USE_PIC18_DELAY
+#elif defined(U8G_CYPRESS_PSOC5)
+#define USE_PSOC5_DELAY
 #elif defined(__arm__)
 /* do not define anything, all procedures are expected to be defined outside u8glib */
 
@@ -293,6 +295,12 @@ void u8g_10MicroDelay(void)
   __delay_cycles(F_CPU/100000UL);
 }
 #endif
+#if defined USE_PSOC5_DELAY
+  #include <project.h>
+  void u8g_Delay(uint16_t val)  {CyDelay(val);};
+  void u8g_MicroDelay(void)     {CyDelay(1);};
+  void u8g_10MicroDelay(void)   {CyDelay(10);};  
+#endif
 
 
 /*== Any other systems: Dummy Delay ==*/

csrc/u8g_dev_ssd1325_nhd27oled_gr_new.c

@@ -220,6 +220,7 @@ static uint8_t u8g_dev_ssd1325_nhd27oled_2x_gr_fn(u8g_t *u8g, u8g_dev_t *dev, ui
 
 U8G_PB_DEV(u8g_dev_ssd1325_nhd27oled_gr_sw_spi , WIDTH, HEIGHT, 4, u8g_dev_ssd1325_nhd27oled_gr_fn, U8G_COM_SW_SPI);
 U8G_PB_DEV(u8g_dev_ssd1325_nhd27oled_gr_hw_spi , WIDTH, HEIGHT, 4, u8g_dev_ssd1325_nhd27oled_gr_fn, U8G_COM_HW_SPI);
+U8G_PB_DEV(u8g_dev_ssd1325_nhd27oled_gr_parallel , WIDTH, HEIGHT, 4, u8g_dev_ssd1325_nhd27oled_gr_fn, U8G_COM_FAST_PARALLEL);
 
 uint8_t u8g_dev_ssd1325_nhd27oled_2x_buf[WIDTH*2] U8G_NOCOMMON ; 
 u8g_pb_t u8g_dev_ssd1325_nhd27oled_2x_pb = { {8, HEIGHT, 0, 0, 0},  WIDTH, u8g_dev_ssd1325_nhd27oled_2x_buf};