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Modified tests for the following builtins:
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__builtin_riscv_cv_simd_extract_h
__builtin_riscv_cv_simd_extract_b
__builtin_riscv_cv_simd_extractu_h
__builtin_riscv_cv_simd_extractu_b
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@adeel10x @PaoloS02
adeel10x authored and PaoloS02 committed Dec 27, 2023
1 parent 058b601 commit e93f95c
Showing 1 changed file with 80 additions and 32 deletions.
112 changes: 80 additions & 32 deletions clang/test/CodeGen/RISCV/corev-intrinsics/simd.c
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Original file line number Diff line number Diff line change
Expand Up @@ -2256,100 +2256,148 @@ uint32_t test_sdotsp_sci_b_negative(uint32_t a, uint8_t b) {
return __builtin_riscv_cv_simd_sdotsp_sc_b(a, -32, b);
}

// CHECK-LABEL: @test_extract_h(
// CHECK-LABEL: @test_extract_h0(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK-NEXT: store i32 [[A:%.*]], ptr [[A_ADDR]], align 4
// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.riscv.cv.simd.extract.h(i32 [[TMP0]], i32 5)
// CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.riscv.cv.simd.extract.h(i32 [[TMP0]], i32 0)
// CHECK-NEXT: ret i32 [[TMP1]]
//
uint32_t test_extract_h(uint32_t a) {
return __builtin_riscv_cv_simd_extract_h(a, 5);
uint32_t test_extract_h0(uint32_t a) {
return __builtin_riscv_cv_simd_extract_h(a, 0);
}

// CHECK-LABEL: @test_extract_h_negative(
// CHECK-LABEL: @test_extract_h1(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK-NEXT: store i32 [[A:%.*]], ptr [[A_ADDR]], align 4
// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.riscv.cv.simd.extract.h(i32 [[TMP0]], i32 224)
// CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.riscv.cv.simd.extract.h(i32 [[TMP0]], i32 1)
// CHECK-NEXT: ret i32 [[TMP1]]
//
uint32_t test_extract_h_negative(uint32_t a) {
return __builtin_riscv_cv_simd_extract_h(a, -32);
uint32_t test_extract_h1(uint32_t a) {
return __builtin_riscv_cv_simd_extract_h(a, 1);
}

// CHECK-LABEL: @test_extract_b(
// CHECK-LABEL: @test_extract_b0(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK-NEXT: store i32 [[A:%.*]], ptr [[A_ADDR]], align 4
// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.riscv.cv.simd.extract.b(i32 [[TMP0]], i32 5)
// CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.riscv.cv.simd.extract.b(i32 [[TMP0]], i32 0)
// CHECK-NEXT: ret i32 [[TMP1]]
//
uint32_t test_extract_b(uint32_t a) {
return __builtin_riscv_cv_simd_extract_b(a, 5);
uint32_t test_extract_b0(uint32_t a) {
return __builtin_riscv_cv_simd_extract_b(a, 0);
}

// CHECK-LABEL: @test_extract_b_negative(
// CHECK-LABEL: @test_extract_b1(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK-NEXT: store i32 [[A:%.*]], ptr [[A_ADDR]], align 4
// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.riscv.cv.simd.extract.b(i32 [[TMP0]], i32 224)
// CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.riscv.cv.simd.extract.b(i32 [[TMP0]], i32 1)
// CHECK-NEXT: ret i32 [[TMP1]]
//
uint32_t test_extract_b_negative(uint32_t a) {
return __builtin_riscv_cv_simd_extract_b(a, -32);
uint32_t test_extract_b1(uint32_t a) {
return __builtin_riscv_cv_simd_extract_b(a, 1);
}

// CHECK-LABEL: @test_extractu_h(
// CHECK-LABEL: @test_extract_b2(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK-NEXT: store i32 [[A:%.*]], ptr [[A_ADDR]], align 4
// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.riscv.cv.simd.extractu.h(i32 [[TMP0]], i32 5)
// CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.riscv.cv.simd.extract.b(i32 [[TMP0]], i32 2)
// CHECK-NEXT: ret i32 [[TMP1]]
//
uint32_t test_extractu_h(uint32_t a) {
return __builtin_riscv_cv_simd_extractu_h(a, 5);
uint32_t test_extract_b2(uint32_t a) {
return __builtin_riscv_cv_simd_extract_b(a, 2);
}

// CHECK-LABEL: @test_extractu_h_negative(
// CHECK-LABEL: @test_extract_b3(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK-NEXT: store i32 [[A:%.*]], ptr [[A_ADDR]], align 4
// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.riscv.cv.simd.extractu.h(i32 [[TMP0]], i32 224)
// CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.riscv.cv.simd.extract.b(i32 [[TMP0]], i32 3)
// CHECK-NEXT: ret i32 [[TMP1]]
//
uint32_t test_extractu_h_negative(uint32_t a) {
return __builtin_riscv_cv_simd_extractu_h(a, -32);
uint32_t test_extract_b3(uint32_t a) {
return __builtin_riscv_cv_simd_extract_b(a, 3);
}

// CHECK-LABEL: @test_extractu_b(
// CHECK-LABEL: @test_extractu_h0(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK-NEXT: store i32 [[A:%.*]], ptr [[A_ADDR]], align 4
// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.riscv.cv.simd.extractu.b(i32 [[TMP0]], i32 5)
// CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.riscv.cv.simd.extractu.h(i32 [[TMP0]], i32 0)
// CHECK-NEXT: ret i32 [[TMP1]]
//
uint32_t test_extractu_b(uint32_t a) {
return __builtin_riscv_cv_simd_extractu_b(a, 5);
uint32_t test_extractu_h0(uint32_t a) {
return __builtin_riscv_cv_simd_extractu_h(a, 0);
}

// CHECK-LABEL: @test_extractu_b_negative(
// CHECK-LABEL: @test_extractu_h1(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK-NEXT: store i32 [[A:%.*]], ptr [[A_ADDR]], align 4
// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.riscv.cv.simd.extractu.b(i32 [[TMP0]], i32 224)
// CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.riscv.cv.simd.extractu.h(i32 [[TMP0]], i32 1)
// CHECK-NEXT: ret i32 [[TMP1]]
//
uint32_t test_extractu_b_negative(uint32_t a) {
return __builtin_riscv_cv_simd_extractu_b(a, -32);
uint32_t test_extractu_h1(uint32_t a) {
return __builtin_riscv_cv_simd_extractu_h(a, 1);
}

// CHECK-LABEL: @test_extractu_b0(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK-NEXT: store i32 [[A:%.*]], ptr [[A_ADDR]], align 4
// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.riscv.cv.simd.extractu.b(i32 [[TMP0]], i32 0)
// CHECK-NEXT: ret i32 [[TMP1]]
//
uint32_t test_extractu_b0(uint32_t a) {
return __builtin_riscv_cv_simd_extractu_b(a, 0);
}

// CHECK-LABEL: @test_extractu_b1(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK-NEXT: store i32 [[A:%.*]], ptr [[A_ADDR]], align 4
// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.riscv.cv.simd.extractu.b(i32 [[TMP0]], i32 1)
// CHECK-NEXT: ret i32 [[TMP1]]
//
uint32_t test_extractu_b1(uint32_t a) {
return __builtin_riscv_cv_simd_extractu_b(a, 1);
}

// CHECK-LABEL: @test_extractu_b2(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK-NEXT: store i32 [[A:%.*]], ptr [[A_ADDR]], align 4
// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.riscv.cv.simd.extractu.b(i32 [[TMP0]], i32 2)
// CHECK-NEXT: ret i32 [[TMP1]]
//
uint32_t test_extractu_b2(uint32_t a) {
return __builtin_riscv_cv_simd_extractu_b(a, 2);
}

// CHECK-LABEL: @test_extractu_b3(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK-NEXT: store i32 [[A:%.*]], ptr [[A_ADDR]], align 4
// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
// CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.riscv.cv.simd.extractu.b(i32 [[TMP0]], i32 3)
// CHECK-NEXT: ret i32 [[TMP1]]
//
uint32_t test_extractu_b3(uint32_t a) {
return __builtin_riscv_cv_simd_extractu_b(a, 3);
}

// CHECK-LABEL: @test_shuffle_h(
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