IRQ arrive on the last instruction of HW loop #107

openhwgroup · Sep 19, 2019 · 78c4c44 · 78c4c44
1 parent f7d6bde
commit 78c4c44
Showing 1 changed file with 2 additions and 2 deletions.
diff --git a/rtl/riscv_fetch_fifo.sv b/rtl/riscv_fetch_fifo.sv
@@ -80,8 +80,8 @@ module riscv_fetch_fifo
 
   assign unaligned_is_compressed    = rdata[17:16] != 2'b11;
   assign aligned_is_compressed      = rdata[1:0] != 2'b11;
-  assign unaligned_is_compressed_st = rdata_Q[0][17:16] != 2'b11;
-  assign aligned_is_compressed_st   = rdata_Q[0][1:0] != 2'b11;
+  assign unaligned_is_compressed_st = valid_Q[0] && rdata_Q[0][17:16] != 2'b11;
+  assign aligned_is_compressed_st   = valid_Q[0] && rdata_Q[0][1:0] != 2'b11;
 
   //////////////////////////////////////////////////////////////////////////////
   // instruction aligner (if unaligned)