Merge pull request #878 from YoannPruvost/dev_rvfi_trace_and_mstatus

RVFI - Better trace log + better mstatus

bhv/cv32e40p_rvfi.sv

@@ -90,8 +90,10 @@ module cv32e40p_rvfi
     // Register reads
     input logic [ 5:0]       rs1_addr_id_i,
     input logic [ 5:0]       rs2_addr_id_i,
+    input logic [ 5:0]       rs3_addr_id_i,
     input logic [31:0]       operand_a_fw_id_i,
     input logic [31:0]       operand_b_fw_id_i,
+    input logic [31:0]       operand_c_fw_id_i,
 
     //// EX probes ////
 
@@ -338,14 +340,19 @@ module cv32e40p_rvfi
     output logic [31:0] rvfi_frd_wdata  [1:0],
     output logic [ 4:0] rvfi_rs1_addr,
     output logic [ 4:0] rvfi_rs2_addr,
+    output logic [ 4:0] rvfi_rs3_addr,
     output logic [31:0] rvfi_rs1_rdata,
     output logic [31:0] rvfi_rs2_rdata,
+    output logic [31:0] rvfi_rs3_rdata,
     output logic [ 4:0] rvfi_frs1_addr,
     output logic [ 4:0] rvfi_frs2_addr,
+    output logic [ 4:0] rvfi_frs3_addr,
     output logic        rvfi_frs1_rvalid,
     output logic        rvfi_frs2_rvalid,
+    output logic        rvfi_frs3_rvalid,
     output logic [31:0] rvfi_frs1_rdata,
     output logic [31:0] rvfi_frs2_rdata,
+    output logic [31:0] rvfi_frs3_rdata,
 
     output logic [31:0] rvfi_pc_rdata,
     output logic [31:0] rvfi_pc_wdata,
@@ -638,7 +645,7 @@ insn_trace_t trace_if, trace_id, trace_ex, trace_ex_next, trace_wb;
         new_rvfi_trace = new();
         new_rvfi_trace.copy_full(wb_bypass_trace_q.pop_front());
         if (next_send == new_rvfi_trace.m_order) begin
-          new_rvfi_trace.m_csr.mstatus_rdata = r_pipe_freeze_trace.csr.mstatus_full_n;
+          new_rvfi_trace.m_csr.mstatus_fs_rdata = r_pipe_freeze_trace.csr.mstatus_fs_n;
           rvfi_trace_q.push_back(new_rvfi_trace);
           next_send = next_send + 1;
         end else begin
@@ -733,12 +740,17 @@ insn_trace_t trace_if, trace_id, trace_ex, trace_ex_next, trace_wb;
     rvfi_rs1_rdata   = '0;
     rvfi_rs2_addr    = '0;
     rvfi_rs2_rdata   = '0;
+    rvfi_rs3_addr    = '0;
+    rvfi_rs3_rdata   = '0;
     rvfi_frs1_rvalid = '0;
     rvfi_frs1_addr   = '0;
     rvfi_frs1_rdata  = '0;
     rvfi_frs2_rvalid = '0;
     rvfi_frs2_addr   = '0;
     rvfi_frs2_rdata  = '0;
+    rvfi_frs3_rvalid = '0;
+    rvfi_frs3_addr   = '0;
+    rvfi_frs3_rdata  = '0;
 
     if (new_rvfi_trace.m_rs1_addr[5]) begin
       rvfi_frs1_rvalid = 1'b1;
@@ -758,6 +770,15 @@ insn_trace_t trace_if, trace_id, trace_ex, trace_ex_next, trace_wb;
       rvfi_rs2_rdata = new_rvfi_trace.m_rs2_rdata;
     end
 
+    if (new_rvfi_trace.m_rs3_addr[5]) begin
+      rvfi_frs3_rvalid = 1'b1;
+      rvfi_frs3_addr   = new_rvfi_trace.m_rs3_addr[4:0];
+      rvfi_frs3_rdata  = new_rvfi_trace.m_rs3_rdata;
+    end else begin
+      rvfi_rs3_addr  = new_rvfi_trace.m_rs3_addr[4:0];
+      rvfi_rs3_rdata = new_rvfi_trace.m_rs3_rdata;
+    end
+
     rvfi_frd_wvalid[0] = '0;
     rvfi_frd_addr[0]   = '0;
     rvfi_frd_wdata[0]  = '0;
@@ -815,7 +836,58 @@ insn_trace_t trace_if, trace_id, trace_ex, trace_ex_next, trace_wb;
     end
 
     //CSR
-    `SET_RVFI_CSR_FROM_INSN(mstatus)
+    rvfi_csr_mstatus_rmask = new_rvfi_trace.m_csr.mstatus_rmask | new_rvfi_trace.m_csr.mstatus_fs_rmask;
+    rvfi_csr_mstatus_wmask = new_rvfi_trace.m_csr.mstatus_wmask;
+    rvfi_csr_mstatus_wmask[31] = new_rvfi_trace.m_csr.mstatus_fs_wmask[31];
+    rvfi_csr_mstatus_wmask[14:13] = new_rvfi_trace.m_csr.mstatus_fs_wmask[14:13];
+
+    if (FPU == 1 && ZFINX == 0) begin
+      rvfi_csr_mstatus_rdata[31] = (new_rvfi_trace.m_csr.mstatus_fs_rdata == FS_DIRTY) ? 1'b1 : 1'b0;
+    end else begin
+      rvfi_csr_mstatus_rdata[31] = '0;
+    end
+    rvfi_csr_mstatus_rdata[30:18] = '0;
+    rvfi_csr_mstatus_rdata[17] = new_rvfi_trace.m_csr.mstatus_rdata.mprv;
+    rvfi_csr_mstatus_rdata[16:15] = '0;
+    if (FPU == 1 && ZFINX == 0) begin
+      rvfi_csr_mstatus_rdata[14:13] = new_rvfi_trace.m_csr.mstatus_fs_rdata;
+    end else begin
+      rvfi_csr_mstatus_rdata[14:13] = '0;
+    end
+    rvfi_csr_mstatus_rdata[12:11] = new_rvfi_trace.m_csr.mstatus_rdata.mpp;
+    rvfi_csr_mstatus_rdata[10:8] = '0;
+    rvfi_csr_mstatus_rdata[7] = new_rvfi_trace.m_csr.mstatus_rdata.mpie;
+    rvfi_csr_mstatus_rdata[6:5] = '0;
+    rvfi_csr_mstatus_rdata[4] = new_rvfi_trace.m_csr.mstatus_rdata.upie;
+    rvfi_csr_mstatus_rdata[3] = new_rvfi_trace.m_csr.mstatus_rdata.mie;
+    rvfi_csr_mstatus_rdata[2:1] = '0;
+    rvfi_csr_mstatus_rdata[0] = new_rvfi_trace.m_csr.mstatus_rdata.uie;
+
+    if (FPU == 1 && ZFINX == 0) begin
+      rvfi_csr_mstatus_wdata[31] = (new_rvfi_trace.m_csr.mstatus_fs_wdata == FS_DIRTY) ? 1'b1 : 1'b0;
+    end else begin
+      rvfi_csr_mstatus_wdata[31] = '0;
+    end
+    rvfi_csr_mstatus_wdata[30:18] = '0;
+    // MPRV is not implemented in the target configuration, writes to it are ignored
+    rvfi_csr_mstatus_wdata[17] = 1'b0;//new_rvfi_trace.m_csr.mstatus_wdata.mprv;
+    rvfi_csr_mstatus_wdata[16:15] = '0;
+    if (FPU == 1 && ZFINX == 0) begin
+      rvfi_csr_mstatus_wdata[14:13] = new_rvfi_trace.m_csr.mstatus_fs_wdata;
+    end else begin
+      rvfi_csr_mstatus_wdata[14:13] = '0;
+    end
+    rvfi_csr_mstatus_wdata[12:11] = new_rvfi_trace.m_csr.mstatus_wdata.mpp;
+    rvfi_csr_mstatus_wdata[10:8] = '0;
+    rvfi_csr_mstatus_wdata[7] = new_rvfi_trace.m_csr.mstatus_wdata.mpie;
+    rvfi_csr_mstatus_wdata[6:5] = '0;
+    // UPIE is not implemented in the target configuration, writes to it are ignored
+    rvfi_csr_mstatus_wdata[4] = 1'b0;//new_rvfi_trace.m_csr.mstatus_wdata.upie;
+    rvfi_csr_mstatus_wdata[3] = new_rvfi_trace.m_csr.mstatus_wdata.mie;
+    rvfi_csr_mstatus_wdata[2:1] = '0;
+    // UIE is not implemented in the target configuration, writes to it are ignored
+    rvfi_csr_mstatus_wdata[0] = 1'b0;//new_rvfi_trace.m_csr.mstatus_wdata.uie;
+
     `SET_RVFI_CSR_FROM_INSN(misa)
     `SET_RVFI_CSR_FROM_INSN(mie)
     `SET_RVFI_CSR_FROM_INSN(mtvec)
@@ -825,7 +897,9 @@ insn_trace_t trace_if, trace_id, trace_ex, trace_ex_next, trace_wb;
     `SET_RVFI_CSR_FROM_INSN(mcause)
     `SET_RVFI_CSR_FROM_INSN(minstret)
     `SET_RVFI_CSR_FROM_INSN(mip)
-
+    // if(rvfi_order == 64'h00000000_00000167) begin
+    //     rvfi_csr_mip_rdata = 32'h0010_0000;
+    // end
     rvfi_csr_tdata_rdata[0] = 'Z;
     rvfi_csr_tdata_rmask[0] = '0;  // Does not exist
     rvfi_csr_tdata_wdata[0] = 'Z;  // Does not exist
@@ -916,14 +990,6 @@ insn_trace_t trace_if, trace_id, trace_ex, trace_ex_next, trace_wb;
     trace_id.m_csr.mtvec_wmask = r_pipe_freeze_trace.csr.mtvec_we ? '1 : '0;
   endfunction
 
-  function void mstatus_to_id();
-    trace_id.m_csr.mstatus_we    = r_pipe_freeze_trace.csr.mstatus_we;
-    trace_id.m_csr.mstatus_rdata = r_pipe_freeze_trace.csr.mstatus_full_q;
-    trace_id.m_csr.mstatus_rmask = '1;
-    trace_id.m_csr.mstatus_wdata = r_pipe_freeze_trace.csr.mstatus_full_n;
-    trace_id.m_csr.mstatus_wmask = r_pipe_freeze_trace.csr.mstatus_we ? '1 : '0;
-  endfunction
-
   function void dcsr_to_id();
     trace_id.m_csr.dcsr_wdata = trace_id.m_csr.dcsr_we ? trace_id.m_csr.dcsr_wdata : r_pipe_freeze_trace.csr.dcsr_n;
     trace_id.m_csr.dcsr_we = r_pipe_freeze_trace.csr.dcsr_we | trace_id.m_csr.dcsr_we;
@@ -1045,14 +1111,20 @@ insn_trace_t trace_if, trace_id, trace_ex, trace_ex_next, trace_wb;
    * The third updates the rvfi interface
    */
   `define CSR_FROM_PIPE(TRACE_NAME, CSR_NAME) \
-    if (r_pipe_freeze_trace.csr.``CSR_NAME``_we || r_pipe_freeze_trace.csr.we) begin \
+    if (r_pipe_freeze_trace.csr.``CSR_NAME``_we) begin \
       trace_``TRACE_NAME``.m_csr.``CSR_NAME``_we      = r_pipe_freeze_trace.csr.``CSR_NAME``_we; \
       trace_``TRACE_NAME``.m_csr.``CSR_NAME``_wdata   = r_pipe_freeze_trace.csr.``CSR_NAME``_n; \
       trace_``TRACE_NAME``.m_csr.``CSR_NAME``_wmask   = '1; \
     end \
     trace_``TRACE_NAME``.m_csr.``CSR_NAME``_rdata   = r_pipe_freeze_trace.csr.``CSR_NAME``_q; \
     trace_``TRACE_NAME``.m_csr.``CSR_NAME``_rmask   = '1;
 
+  event e_mstatus_to_id;
+  function void mstatus_to_id();
+    `CSR_FROM_PIPE(id, mstatus)
+    `CSR_FROM_PIPE(id, mstatus_fs)
+    ->e_mstatus_to_id;
+  endfunction
   //those event are for debug purpose
   event e_dev_send_wb_1, e_dev_send_wb_2;
   event
@@ -1088,14 +1160,11 @@ insn_trace_t trace_if, trace_id, trace_ex, trace_ex_next, trace_wb;
     `CSR_FROM_PIPE(apu_resp, fcsr)
     `CSR_FROM_PIPE(apu_resp, fflags)
 
-    trace_apu_resp.m_csr.mstatus_we    = r_pipe_freeze_trace.csr.mstatus_we;
-    trace_apu_resp.m_csr.mstatus_rdata = r_pipe_freeze_trace.csr.mstatus_full_q;
-    trace_apu_resp.m_csr.mstatus_rmask = '1;
-    trace_apu_resp.m_csr.mstatus_wdata = r_pipe_freeze_trace.csr.mstatus_full_n;
-    trace_apu_resp.m_csr.mstatus_wmask = r_pipe_freeze_trace.csr.mstatus_we ? '1 : '0;
+    // `CSR_FROM_PIPE(apu_resp, mstatus)
+    `CSR_FROM_PIPE(apu_resp, mstatus_fs)
 
     if (r_pipe_freeze_trace.csr.mstatus_we) begin
-      trace_ex.m_csr.mstatus_rdata = r_pipe_freeze_trace.csr.mstatus_full_n;
+      trace_ex.m_csr.mstatus_fs_rdata = r_pipe_freeze_trace.csr.mstatus_fs_n;
     end
   endfunction
 
@@ -1720,8 +1789,10 @@ insn_trace_t trace_if, trace_id, trace_ex, trace_ex_next, trace_wb;
     rvfi_rd_wdata[1] = '0;
     rvfi_rs1_addr    = '0;
     rvfi_rs2_addr    = '0;
+    rvfi_rs3_addr    = '0;
     rvfi_rs1_rdata   = '0;
     rvfi_rs2_rdata   = '0;
+    rvfi_rs3_rdata   = '0;
     rvfi_mem_addr    = '0;
     rvfi_mem_rmask   = '0;
     rvfi_mem_wmask   = '0;

bhv/cv32e40p_rvfi_trace.sv

@@ -45,15 +45,20 @@ module cv32e40p_rvfi_trace
 
     input logic [ 4:0] rvfi_rs1_addr,
     input logic [ 4:0] rvfi_rs2_addr,
+    input logic [ 4:0] rvfi_rs3_addr,
     input logic [31:0] rvfi_rs1_rdata,
     input logic [31:0] rvfi_rs2_rdata,
+    input logic [31:0] rvfi_rs3_rdata,
 
     input logic [ 4:0] rvfi_frs1_addr,
     input logic [ 4:0] rvfi_frs2_addr,
+    input logic [ 4:0] rvfi_frs3_addr,
     input logic        rvfi_frs1_rvalid,
     input logic        rvfi_frs2_rvalid,
+    input logic        rvfi_frs3_rvalid,
     input logic [31:0] rvfi_frs1_rdata,
     input logic [31:0] rvfi_frs2_rdata,
+    input logic [31:0] rvfi_frs3_rdata,
 
     input logic [31:0] rvfi_mem_addr,
     input logic [ 3:0] rvfi_mem_rmask,
@@ -112,16 +117,22 @@ module cv32e40p_rvfi_trace
       rs2_value = rvfi_rs2_rdata;
     end
 
+    if (rvfi_frs3_rvalid) begin
+      rs3 = {1'b1, rvfi_frs3_addr};
+      rs3_value = rvfi_frs3_rdata;
+    end else begin
+      rs3 = {1'b0, rvfi_rs3_addr};
+      rs3_value = rvfi_rs3_rdata;
+    end
+
     if (rvfi_frd_wvalid[0]) begin
       rd = {1'b1, rvfi_frd_addr[0]};
     end else begin
       rd = {1'b0, rvfi_rd_addr[0]};
     end
   end
 
-  assign rs3 = '0;
-  assign rs4 = '0;
-  assign rs3_value = rvfi_rd_wdata[0];
+  assign rs4 = rs3;
 
   assign imm_i_type = {{20{rvfi_insn[31]}}, rvfi_insn[31:20]};
   assign imm_iz_type = {20'b0, rvfi_insn[31:20]};
@@ -163,10 +174,14 @@ instr_trace_t trace_retire;
 
   function void apply_reg_write();
     foreach (trace_retire.regs_write[i]) begin
-      if (trace_retire.regs_write[i].addr == rvfi_rd_addr[0]) begin
+      if (rvfi_frd_wvalid[0] && (trace_retire.regs_write[i].addr == {1'b1, rvfi_frd_addr[0]})) begin
+        trace_retire.regs_write[i].value = rvfi_frd_wdata[0];
+      end else if (trace_retire.regs_write[i].addr == rvfi_rd_addr[0]) begin
         trace_retire.regs_write[i].value = rvfi_rd_wdata[0];
       end
-      if (trace_retire.regs_write[i].addr == rvfi_rd_addr[1]) begin
+      if (rvfi_frd_wvalid[1] && (trace_retire.regs_write[i].addr == {1'b1, rvfi_frd_addr[1]})) begin
+        trace_retire.regs_write[i].value = rvfi_frd_wdata[1];
+      end else if (trace_retire.regs_write[i].addr == rvfi_rd_addr[1]) begin
         trace_retire.regs_write[i].value = rvfi_rd_wdata[1];
       end
     end

bhv/cv32e40p_tb_wrapper.sv

@@ -272,8 +272,10 @@ module cv32e40p_tb_wrapper
 
       .rs1_addr_id_i     (cv32e40p_top_i.core_i.id_stage_i.regfile_addr_ra_id),
       .rs2_addr_id_i     (cv32e40p_top_i.core_i.id_stage_i.regfile_addr_rb_id),
+      .rs3_addr_id_i     (cv32e40p_top_i.core_i.id_stage_i.regfile_addr_rc_id),
       .operand_a_fw_id_i (cv32e40p_top_i.core_i.id_stage_i.operand_a_fw_id),
       .operand_b_fw_id_i (cv32e40p_top_i.core_i.id_stage_i.operand_b_fw_id),
+      .operand_c_fw_id_i (cv32e40p_top_i.core_i.id_stage_i.operand_c_fw_id),
       // .instr         (cv32e40p_top_i.core_i.id_stage_i.instr     ),
       .is_compressed_id_i(cv32e40p_top_i.core_i.id_stage_i.is_compressed_i),
       .ebrk_insn_dec_i   (cv32e40p_top_i.core_i.id_stage_i.ebrk_insn_dec),
@@ -452,14 +454,19 @@ module cv32e40p_tb_wrapper
       .rvfi_frd_wdata(rvfi_frd_wdata),
       .rvfi_rs1_addr(rvfi_rs1_addr),
       .rvfi_rs2_addr(rvfi_rs2_addr),
+      .rvfi_rs3_addr(rvfi_rs3_addr),
       .rvfi_rs1_rdata(rvfi_rs1_rdata),
       .rvfi_rs2_rdata(rvfi_rs2_rdata),
+      .rvfi_rs3_rdata(rvfi_rs3_rdata),
       .rvfi_frs1_addr(rvfi_frs1_addr),
       .rvfi_frs2_addr(rvfi_frs2_addr),
+      .rvfi_frs3_addr(rvfi_frs3_addr),
       .rvfi_frs1_rvalid(rvfi_frs1_rvalid),
       .rvfi_frs2_rvalid(rvfi_frs2_rvalid),
+      .rvfi_frs3_rvalid(rvfi_frs3_rvalid),
       .rvfi_frs1_rdata(rvfi_frs1_rdata),
       .rvfi_frs2_rdata(rvfi_frs2_rdata),
+      .rvfi_frs3_rdata(rvfi_frs3_rdata),
       .rvfi_mem_addr(rvfi_mem_addr),
       .rvfi_mem_rmask(rvfi_mem_rmask),
       .rvfi_mem_wmask(rvfi_mem_wmask),

bhv/insn_trace.sv

@@ -46,8 +46,10 @@
     logic       m_fcsr_we_non_apu;
     logic [5:0] m_rs1_addr;
     logic [5:0] m_rs2_addr;
+    logic [5:0] m_rs3_addr;
     logic [31:0] m_rs1_rdata;
     logic [31:0] m_rs2_rdata;
+    logic [31:0] m_rs3_rdata;
 
     bit m_trap;
 
@@ -71,7 +73,17 @@
     } m_mem;
 
     struct {
-      `DEFINE_CSR(mstatus)
+      logic mstatus_we;
+      logic [31:0] mstatus_rmask;
+      Status_t mstatus_wdata;
+      logic [31:0] mstatus_wmask;
+      Status_t mstatus_rdata;
+
+      logic mstatus_fs_we;
+      FS_t mstatus_fs_rdata;
+      logic [31:0] mstatus_fs_rmask;
+      FS_t mstatus_fs_wdata;
+      logic [31:0] mstatus_fs_wmask;
 
       // mstatush
 
@@ -161,6 +173,7 @@
 
     function void init_csr();
       `INIT_CSR(mstatus)
+      `INIT_CSR(mstatus_fs)
       `INIT_CSR(misa)
       `INIT_CSR(mie)
       `INIT_CSR(mtvec)
@@ -222,6 +235,7 @@
       this.m_2_rd_insn         = 1'b0;
       this.m_rs1_addr          = '0;
       this.m_rs2_addr          = '0;
+      this.m_rs3_addr          = '0;
       this.m_ex_fw             = '0;
       this.m_csr.got_minstret  = '0;
       this.m_dbg_taken         = '0;
@@ -245,8 +259,10 @@
 
       this.m_rs1_addr  = r_pipe_freeze_trace.rs1_addr_id;
       this.m_rs2_addr  = r_pipe_freeze_trace.rs2_addr_id;
+      this.m_rs3_addr  = r_pipe_freeze_trace.rs3_addr_id;
       this.m_rs1_rdata = r_pipe_freeze_trace.operand_a_fw_id;
       this.m_rs2_rdata = r_pipe_freeze_trace.operand_b_fw_id;
+      this.m_rs3_rdata = r_pipe_freeze_trace.operand_c_fw_id;
 
       this.m_mem.addr    = '0;
       this.m_mem.rmask   = '0;
@@ -287,8 +303,10 @@
       this.m_instret_cnt        = m_source.m_instret_cnt;
       this.m_rs1_addr           = m_source.m_rs1_addr;
       this.m_rs2_addr           = m_source.m_rs2_addr;
+      this.m_rs3_addr           = m_source.m_rs3_addr;
       this.m_rs1_rdata          = m_source.m_rs1_rdata;
       this.m_rs2_rdata          = m_source.m_rs2_rdata;
+      this.m_rs3_rdata          = m_source.m_rs3_rdata;
 
       this.m_ex_fw              = m_source.m_ex_fw;
       this.m_rd_addr            = m_source.m_rd_addr;
@@ -304,6 +322,7 @@
       this.m_mem                = m_source.m_mem;
       //CRS
       `ASSIGN_CSR(mstatus)
+      `ASSIGN_CSR(mstatus_fs)
       `ASSIGN_CSR(misa)
       `ASSIGN_CSR(mie)
       `ASSIGN_CSR(mtvec)