HWloop end CSR updated by a cancelled cv.end instruction

[pascalgouedo]

Issue Description

HWloop end address CSR is updated while there is a trigger match on cv.end instruction which should prevent any CSR update.

Component

Component:RTL

Steps to Reproduce

As shown below, the following sequence happens:

• debug_req at time 2
• Core going to debug mode at time 10
• Trigger tdata1 register written enabling "match instruction address" at time 14
• dret executed at time 16 putting back the Core in running mode at time 22
• instruction fetch from address 0x0 (pc_if = depc) at time 22
• cv.end in ID stage firing trigger_match_o (pc_id == tmatch_value_q) at time 24
• ID instruction cancelled by halt_id (id_valid = 0) at time 24
• Core going in debug mode at time 30

While cv.end should be cancelled and have no effect on CSRs, hwlp_we_i[1] is still asserted at time 24 and updates hwlp_end_q the cycle after.

Top Level Parameters

cv32e40p_wrapper #(
    .PULP_XPULP       (1),
    .PULP_CLUSTER     (0),
    .FPU              (0),
    .PULP_ZFINX       (0),
    .NUM_MHPMCOUNTERS (1)
)

Git hash: ebdbbb7

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Product: OneSpin 360 DV-Verify
App: Processor Verification App
Tool's version: 2023.3_1

[pascalgouedo]

Corrected with PR #897