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Automatic PR dev->master #899

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Nov 7, 2023
Merged

Automatic PR dev->master #899

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1042a85
Issue #888 correction
Oct 10, 2023
80160c5
Issue #887 correction
Oct 10, 2023
206a4ba
Reduced line length.
Oct 10, 2023
ba2f67c
Issue #889 correction.
Oct 18, 2023
34977aa
Added a note about MSTATUS.FS update.
Oct 19, 2023
ac4bb22
Reduce line length.
Oct 23, 2023
7c2bb28
Corrected MPIE/MPP mode.
Oct 24, 2023
f88b1c6
Issue #896 correction
Oct 24, 2023
b13c97e
Updated CVFPU release version
Oct 27, 2023
0f3c925
Correction to avoid simulation/implementation tools warning.
Oct 27, 2023
e6f2800
Additional correction for issue #896 to manage MSTATUS.FS write confl…
Nov 6, 2023
688a28a
Merge pull request #897 from pascalgouedo/dev_dd_pgo_rtl
davideschiavone Nov 7, 2023
40f6edf
Merge pull request #898 from pascalgouedo/dev_dd_pgo_doc
davideschiavone Nov 7, 2023
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24 changes: 16 additions & 8 deletions docs/source/control_status_registers.rst
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Expand Up @@ -445,7 +445,7 @@ Detailed:
+-------------+-----------+-------------------------------------------------------------------------------------------------------------------------+
| 30:15 | RO | 0, Unimplemented. |
+-------------+-----------+-------------------------------------------------------------------------------------------------------------------------+
| 14:13 | RW | **FS:** Floating point State |
| 14:13 | RW | **FS:** Floating point State (See note below) |
| | | |
| | | 00 = Off |
| | | |
Expand All @@ -457,13 +457,13 @@ Detailed:
| | | |
| | | 0 if ``FPU`` = 0 or (``FPU`` = 1 and ``ZFINX`` = 1). |
+-------------+-----------+-------------------------------------------------------------------------------------------------------------------------+
| 12:11 | RO | **MPP:** Machine Previous Priviledge mode |
| 12:11 | RW | **MPP:** Machine Previous Priviledge mode |
| | | |
| | | 11 when the user mode is not enabled. |
| | | Hardwired to 11 when the User mode is not enabled. |
+-------------+-----------+-------------------------------------------------------------------------------------------------------------------------+
| 10:8 | RO | 0, Unimplemented. |
+-------------+-----------+-------------------------------------------------------------------------------------------------------------------------+
| 7 | RO | **MPIE:** Machine Previous Interrupt Enable |
| 7 | RW | **MPIE:** Machine Previous Interrupt Enable |
| | | |
| | | When an exception is encountered, MPIE will be set to MIE. |
| | | When the mret instruction is executed, the value of MPIE will be stored to MIE. |
Expand All @@ -478,6 +478,10 @@ Detailed:
| 2:0 | RO | 0, Unimplemented. |
+-------------+-----------+-------------------------------------------------------------------------------------------------------------------------+

.. note::

As allowed by RISC-V ISA and to simplify MSTATUS.FS update in the design, the state is updated to Dirty when executing any F instructions except for all FSW ones.

.. only:: USER

User Status (``ustatus``)
Expand Down Expand Up @@ -652,8 +656,10 @@ Detailed:
| 4:0 | RW | **Exception Code** (See note below) |
+-------------+-----------+----------------------------------------------------------------------------------+

**NOTE**: software accesses to `mcause[4:0]` must be sensitive to the WLRL field specification of this CSR. For example,
when `mcause[31]` is set, writing 0x1 to `mcause[1]` (Supervisor software interrupt) will result in UNDEFINED behavior.
.. note::

Software accesses to `mcause[4:0]` must be sensitive to the WLRL field specification of this CSR. For example,
when `mcause[31]` is set, writing 0x1 to `mcause[1]` (Supervisor software interrupt) will result in UNDEFINED behavior.


Machine Trap Value (``mtval``)
Expand Down Expand Up @@ -1603,8 +1609,10 @@ Detailed:
| 4:0 | RW | **Exception Code** (See note below) |
+-------------+-----------+------------------------------------------------------------------------------------+

**NOTE**: software accesses to `ucause[4:0]` must be sensitive to the WLRL field specification of this CSR. For example,
when `ucause[31]` is set, writing 0x1 to `ucause[1]` (Supervisor software interrupt) will result in UNDEFINED behavior.
.. note::

Software accesses to `ucause[4:0]` must be sensitive to the WLRL field specification of this CSR. For example,
when `ucause[31]` is set, writing 0x1 to `ucause[1]` (Supervisor software interrupt) will result in UNDEFINED behavior.


.. only:: PMP
Expand Down
2 changes: 1 addition & 1 deletion docs/source/fpu.rst
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Expand Up @@ -25,7 +25,7 @@ precision can be enabled by setting the parameter **FPU** of the ``cv32e40p_top`
to 1. This will extend the CV32E40P decoder accordingly and will instantiate the FPU.
The FPU repository used by the CV32E40P is available at `https://github.com/openhwgroup/cvfpu <https://github.com/openhwgroup/cvfpu/tree/3116391bf66660f806b45e212b9949c528b4e270>`_ and
its documentation can be found `here <https://github.com/openhwgroup/cvfpu/blob/3116391bf66660f806b45e212b9949c528b4e270/docs/README.md>`_.
CVFPU v1.0.0 release has been copied in CV32E40P repository inside rtl/vendor (used for verification and implementation) so all core and FPU RTL files should be taken from CV32E40P repository.
CVFPU v0.8.1 release has been copied in CV32E40P repository inside rtl/vendor (used for verification and implementation) so all core and FPU RTL files should be taken from CV32E40P repository.

cv32e40p_fpu_manifest file is listing all necessary files for both the Core and CVFPU.

Expand Down
2 changes: 2 additions & 0 deletions rtl/cv32e40p_controller.sv
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Expand Up @@ -491,6 +491,7 @@ module cv32e40p_controller import cv32e40p_pkg::*;
if ( (debug_req_pending || trigger_match_i) & ~debug_mode_q )
begin
//Serving the debug
is_decoding_o = COREV_PULP ? 1'b0 : 1'b1;
halt_if_o = 1'b1;
halt_id_o = 1'b1;
ctrl_fsm_ns = DBG_FLUSH;
Expand Down Expand Up @@ -712,6 +713,7 @@ module cv32e40p_controller import cv32e40p_pkg::*;
if ( (debug_req_pending || trigger_match_i) & ~debug_mode_q )
begin
//Serving the debug
is_decoding_o = COREV_PULP ? 1'b0 : 1'b1;
halt_if_o = 1'b1;
halt_id_o = 1'b1;
ctrl_fsm_ns = DBG_FLUSH;
Expand Down
23 changes: 16 additions & 7 deletions rtl/cv32e40p_core.sv
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Expand Up @@ -158,6 +158,7 @@ module cv32e40p_core
logic [31:0] jump_target_id, jump_target_ex;
logic branch_in_ex;
logic branch_decision;
logic [ 1:0] ctrl_transfer_insn_in_dec;

logic ctrl_busy;
logic if_busy;
Expand Down Expand Up @@ -201,6 +202,7 @@ module cv32e40p_core
logic [ C_RM-1:0] frm_csr;
logic [ C_FFLAG-1:0] fflags_csr;
logic fflags_we;
logic fregs_we;

// APU
logic apu_en_ex;
Expand Down Expand Up @@ -540,9 +542,10 @@ module cv32e40p_core
.instr_req_o (instr_req_int),

// Jumps and branches
.branch_in_ex_o (branch_in_ex),
.branch_decision_i(branch_decision),
.jump_target_o (jump_target_id),
.branch_in_ex_o (branch_in_ex),
.branch_decision_i (branch_decision),
.jump_target_o (jump_target_id),
.ctrl_transfer_insn_in_dec_o(ctrl_transfer_insn_in_dec),

// IF and ID control signals
.clear_instr_valid_o(clear_instr_valid),
Expand Down Expand Up @@ -785,6 +788,8 @@ module cv32e40p_core
.data_misaligned_ex_i(data_misaligned_ex), // from ID/EX pipeline
.data_misaligned_i (data_misaligned),

.ctrl_transfer_insn_in_dec_i(ctrl_transfer_insn_in_dec),

// FPU
.fpu_fflags_we_o(fflags_we),
.fpu_fflags_o (fflags_csr),
Expand Down Expand Up @@ -969,6 +974,7 @@ module cv32e40p_core
.frm_o (frm_csr),
.fflags_i (fflags_csr),
.fflags_we_i(fflags_we),
.fregs_we_i (fregs_we),

// Interrupt related control signals
.mie_bypass_o (mie_bypass),
Expand Down Expand Up @@ -1037,13 +1043,16 @@ module cv32e40p_core
);

// CSR access
assign csr_addr = csr_addr_int;
assign csr_wdata = alu_operand_a_ex;
assign csr_op = csr_op_ex;
assign csr_addr = csr_addr_int;
assign csr_wdata = alu_operand_a_ex;
assign csr_op = csr_op_ex;

assign csr_addr_int = csr_num_e'(csr_access_ex ? alu_operand_b_ex[11:0] : '0);


// Floating-Point registers write
assign fregs_we = (FPU & !ZFINX) ? ((regfile_alu_we_fw && regfile_alu_waddr_fw[5]) ||
(regfile_we_wb && regfile_waddr_fw_wb_o[5]))
: 1'b0;

///////////////////////////
// ____ __ __ ____ //
Expand Down
8 changes: 6 additions & 2 deletions rtl/cv32e40p_cs_registers.sv
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Expand Up @@ -68,6 +68,7 @@ module cv32e40p_cs_registers
output logic [ 2:0] frm_o,
input logic [C_FFLAG-1:0] fflags_i,
input logic fflags_we_i,
input logic fregs_we_i,

// Interrupts
output logic [31:0] mie_bypass_o,
Expand Down Expand Up @@ -212,6 +213,7 @@ module cv32e40p_cs_registers

logic [31:0] exception_pc;
Status_t mstatus_q, mstatus_n;
logic mstatus_we_int;
FS_t mstatus_fs_q, mstatus_fs_n;
logic [5:0] mcause_q, mcause_n;
logic [5:0] ucause_q, ucause_n;
Expand Down Expand Up @@ -897,6 +899,7 @@ module cv32e40p_cs_registers
dscratch0_n = dscratch0_q;
dscratch1_n = dscratch1_q;

mstatus_we_int = 1'b0;
mstatus_n = mstatus_q;
mcause_n = mcause_q;
ucause_n = '0; // Not used if PULP_SECURE == 0
Expand Down Expand Up @@ -957,7 +960,8 @@ module cv32e40p_cs_registers
mprv: csr_wdata_int[MSTATUS_MPRV_BIT]
};
if (FPU == 1 && ZFINX == 0) begin
mstatus_fs_n = FS_t'(csr_wdata_int[MSTATUS_FS_BIT_HIGH:MSTATUS_FS_BIT_LOW]);
mstatus_we_int = 1'b1;
mstatus_fs_n = FS_t'(csr_wdata_int[MSTATUS_FS_BIT_HIGH:MSTATUS_FS_BIT_LOW]);
end
end
// mie: machine interrupt enable
Expand Down Expand Up @@ -1027,7 +1031,7 @@ module cv32e40p_cs_registers

if (ZFINX == 0) begin
// FPU Register File/Flags implicit update or modified by CSR instructions
if (fflags_we_i || fcsr_update) begin
if ((fregs_we_i && !(mstatus_we_int && mstatus_fs_n != FS_DIRTY)) || fflags_we_i || fcsr_update) begin
mstatus_fs_n = FS_DIRTY;
end
end
Expand Down
22 changes: 19 additions & 3 deletions rtl/cv32e40p_ex_stage.sv
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Expand Up @@ -81,6 +81,8 @@ module cv32e40p_ex_stage
input logic data_misaligned_ex_i,
input logic data_misaligned_i,

input logic [1:0] ctrl_transfer_insn_in_dec_i,

// FPU signals
output logic fpu_fflags_we_o,
output logic [APU_NUSFLAGS_CPU-1:0] fpu_fflags_o,
Expand Down Expand Up @@ -371,19 +373,33 @@ module cv32e40p_ex_stage
apu_result_q <= 'b0;
apu_flags_q <= 'b0;
end else begin
if (apu_rvalid_i && apu_multicycle && (data_misaligned_i || data_misaligned_ex_i || (data_req_i && regfile_alu_we_i) || (mulh_active && (mult_operator_i == MUL_H)))) begin
if (apu_rvalid_i && apu_multicycle &&
(data_misaligned_i || data_misaligned_ex_i ||
((data_req_i || data_rvalid_i) && regfile_alu_we_i) ||
(mulh_active && (mult_operator_i == MUL_H)) ||
((ctrl_transfer_insn_in_dec_i == BRANCH_JALR) &&
regfile_alu_we_i && ~apu_read_dep_for_jalr_o))) begin
apu_rvalid_q <= 1'b1;
apu_result_q <= apu_result_i;
apu_flags_q <= apu_flags_i;
end else if (apu_rvalid_q && !(data_misaligned_i || data_misaligned_ex_i || ((data_req_i || data_rvalid_i) && regfile_alu_we_i) || (mulh_active && (mult_operator_i == MUL_H)))) begin
end else if (apu_rvalid_q && !(data_misaligned_i || data_misaligned_ex_i ||
((data_req_i || data_rvalid_i) && regfile_alu_we_i) ||
(mulh_active && (mult_operator_i == MUL_H)) ||
((ctrl_transfer_insn_in_dec_i == BRANCH_JALR) &&
regfile_alu_we_i && ~apu_read_dep_for_jalr_o))) begin
apu_rvalid_q <= 1'b0;
end
end
end

assign apu_req_o = apu_req;
assign apu_gnt = apu_gnt_i;
assign apu_valid = (apu_multicycle && (data_misaligned_i || data_misaligned_ex_i || ((data_req_i || data_rvalid_i) && regfile_alu_we_i) || (mulh_active && (mult_operator_i == MUL_H)))) ? 1'b0 : (apu_rvalid_i || apu_rvalid_q);
assign apu_valid = (apu_multicycle && (data_misaligned_i || data_misaligned_ex_i ||
((data_req_i || data_rvalid_i) && regfile_alu_we_i) ||
(mulh_active && (mult_operator_i == MUL_H)) ||
((ctrl_transfer_insn_in_dec_i == BRANCH_JALR) &&
regfile_alu_we_i && ~apu_read_dep_for_jalr_o)))
? 1'b0 : (apu_rvalid_i || apu_rvalid_q);
assign apu_operands_o = apu_operands_i;
assign apu_op_o = apu_op_i;
assign apu_result = apu_rvalid_q ? apu_result_q : apu_result_i;
Expand Down
2 changes: 1 addition & 1 deletion rtl/cv32e40p_fp_wrapper.sv
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Expand Up @@ -111,7 +111,7 @@ module cv32e40p_fp_wrapper
.int_fmt_i (fpnew_pkg::int_format_e'(fpu_int_fmt)),
.vectorial_op_i(fpu_vec_op),
.tag_i (1'b0),
.simd_mask_i ('b0),
.simd_mask_i (1'b0),
.in_valid_i (apu_req_i),
.in_ready_o (apu_gnt_o),
.flush_i (1'b0),
Expand Down
5 changes: 3 additions & 2 deletions rtl/cv32e40p_id_stage.sv
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Expand Up @@ -70,6 +70,7 @@ module cv32e40p_id_stage
output logic branch_in_ex_o,
input logic branch_decision_i,
output logic [31:0] jump_target_o,
output logic [ 1:0] ctrl_transfer_insn_in_dec_o,

// IF and ID stage signals
output logic clear_instr_valid_o,
Expand Down Expand Up @@ -1087,7 +1088,7 @@ module cv32e40p_id_stage
.debug_wfi_no_sleep_i(debug_wfi_no_sleep),

// jump/branches
.ctrl_transfer_insn_in_dec_o (ctrl_transfer_insn_in_dec),
.ctrl_transfer_insn_in_dec_o (ctrl_transfer_insn_in_dec_o),
.ctrl_transfer_insn_in_id_o (ctrl_transfer_insn_in_id),
.ctrl_transfer_target_mux_sel_o(ctrl_transfer_target_mux_sel),

Expand Down Expand Up @@ -1187,7 +1188,7 @@ module cv32e40p_id_stage
// jump/branch control
.branch_taken_ex_i (branch_taken_ex),
.ctrl_transfer_insn_in_id_i (ctrl_transfer_insn_in_id),
.ctrl_transfer_insn_in_dec_i(ctrl_transfer_insn_in_dec),
.ctrl_transfer_insn_in_dec_i(ctrl_transfer_insn_in_dec_o),

// Interrupt signals
.irq_wu_ctrl_i (irq_wu_ctrl),
Expand Down
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