Skip to content

GPIO Register access #15342

Answered by robert-hh
Jeff-Squared asked this question in ESP32
Jun 24, 2024 · 1 comments · 1 reply
Discussion options

You must be logged in to vote

The source of this information are the respective Reference Manuals.

The target address is base_address + Offset. The offset for GPIO_OUT_REG is 0x04, for GPIO_ENABLE_REG is 0x20. At the S2, there are two base addresses listed, 0x3f40_4000 and 0x6000_4000, at the S3 I read 0x6000_4000 for the base address.

Replies: 1 comment 1 reply

Comment options

You must be logged in to vote
1 reply
@Jeff-Squared
Comment options

Answer selected by Jeff-Squared
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Category
ESP32
Labels
None yet
2 participants