Different Interface for Software and RTL

[SzymonHitachi]

Is there a possibility to generate different interface for CPU (with all the named fields) while at the same time keeping it as a large vector output for RTL?

So for example I define a field:

it will create a module with o_EXAMPLE_EXAMPLE and o_EXAMPLE_EXAMPLE2 ports, while c header will have separate access to both.
I would like to keep this separate access strucutre in c header but let the RTL to have a single output for whole o_EXAMPLE register.

Is that even possible?

[taichi-ishitani]

Hi @SzymonHitachi ,

You can generate registers having such output port by creating your own plugin to add such register type support.

[SzymonHitachi]

Thank you, I will explore that path

[SzymonHitachi]

But would it be possible to achieve this using something builtin? Like maybe the indirect register? (I'm unsure how it really works after reading the wiki :D )

[taichi-ishitani]

But would it be possible to achieve this using something builtin?

For builtin, there are no such options.

[taichi-ishitani]

You can refer the repositories below for plugin development.

• https://github.com/taichi-ishitani/rice/tree/master/script/rb/rggen-rice
• https://github.com/taichi-ishitani/rggen-spi