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    • chipyard

      Public
      An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
      Scala
      BSD 3-Clause "New" or "Revised" License
      6371.6k17920Updated Oct 14, 2024Oct 14, 2024
    • IsaacLab

      Public
      Unified framework for robot learning built on NVIDIA Isaac Sim
      Python
      Other
      813000Updated Oct 12, 2024Oct 12, 2024
    • HTML
      6750Updated Oct 11, 2024Oct 11, 2024
    • hammer

      Public
      Hammer: Highly Agile Masks Made Effortlessly from RTL
      Python
      BSD 3-Clause "New" or "Revised" License
      5725420318Updated Oct 11, 2024Oct 11, 2024
    • SystemVerilog
      BSD 3-Clause "New" or "Revised" License
      0200Updated Oct 10, 2024Oct 10, 2024
    • dosa

      Public
      DOSA: Differentiable Model-Based One-Loop Search for DNN Accelerators
      Python
      BSD 2-Clause "Simplified" License
      11310Updated Oct 10, 2024Oct 10, 2024
    • Scala
      BSD 3-Clause "New" or "Revised" License
      0000Updated Oct 10, 2024Oct 10, 2024
    • C
      BSD 3-Clause "New" or "Revised" License
      13026Updated Oct 10, 2024Oct 10, 2024
    • Python
      0000Updated Oct 9, 2024Oct 9, 2024
    • Scala
      BSD 3-Clause "New" or "Revised" License
      5980154Updated Oct 9, 2024Oct 9, 2024
    • Rust
      0200Updated Oct 9, 2024Oct 9, 2024
    • Chisel RISC-V Vector 1.0 Implementation
      Assembly
      BSD 3-Clause "New" or "Revised" License
      34521Updated Oct 8, 2024Oct 8, 2024
    • radiance

      Public
      Rocket Chip Generator
      SystemVerilog
      Other
      1.1k100Updated Oct 7, 2024Oct 7, 2024
    • Python
      Other
      0000Updated Oct 7, 2024Oct 7, 2024
    • A tool for converting PyTorch models into raw C codes that can be executed standalone in a baremetal runtime on RISC-V research chips.
      C
      22000Updated Oct 4, 2024Oct 4, 2024
    • shuttle

      Public
      A Rocket-based RISC-V superscalar in-order core
      Scala
      22600Updated Oct 3, 2024Oct 3, 2024
    • Fork of seldridge/rocket-rocc-examples with tests for a systolic array based matmul accelerator
      C
      Other
      385368Updated Sep 30, 2024Sep 30, 2024
    • gemmini

      Public
      Berkeley's Spatial Array Generator
      Scala
      Other
      1627897712Updated Sep 30, 2024Sep 30, 2024
    • RoSE

      Public
      A unified simulation platform that combines hardware and software, enabling pre-silicon, full-stack, closed-loop evaluation of your robotic system.
      Python
      BSD 3-Clause "New" or "Revised" License
      43401Updated Sep 27, 2024Sep 27, 2024
    • Chisel wrapper for the SpinalHDL VexiiRiscv CPU implementation, implementing Chipyard compatibility
      Scala
      BSD 3-Clause "New" or "Revised" License
      0000Updated Sep 26, 2024Sep 26, 2024
    • 0000Updated Sep 26, 2024Sep 26, 2024
    • rerocc

      Public
      Scala
      1710Updated Sep 26, 2024Sep 26, 2024
    • Collection of device models for spike
      C++
      5722Updated Sep 16, 2024Sep 16, 2024
    • Scala
      Other
      87288173Updated Sep 11, 2024Sep 11, 2024
    • 0000Updated Sep 9, 2024Sep 9, 2024
    • Hammer plugins for synopsys tools
      Python
      Other
      1831Updated Sep 9, 2024Sep 9, 2024
    • spyke

      Public
      Spyke, a RISC-V ISA Simulator in Python, for education purpose only, maybe
      0200Updated Sep 7, 2024Sep 7, 2024
    • riskybird

      Public
      C++
      4100Updated Sep 6, 2024Sep 6, 2024
    • pyuartsi

      Public
      A standalone implementation of the Tethered Serial Interface (TSI) in Python.
      Python
      0500Updated Sep 1, 2024Sep 1, 2024
    • A Chisel RTL generator for network-on-chip interconnects
      Scala
      BSD 3-Clause "New" or "Revised" License
      25172203Updated Aug 23, 2024Aug 23, 2024