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I see that stm32f3 and stm32f4 are supported.. how hard would it be to run on stm32f2? Would it be just changing some config file, or more like developing new Hubris components? |
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@cbiffle can certainly answer with more authority, but it shouldn't be too bad -- this is a Cortex-M3, broadly similar to an M4. That said, that it is missing an FPU will surely necessitate some code changes -- for example (speaking from a Humility perspective), stack backtraces (via So: very doable, but will require a modest amount of low-level work -- and should be much easier than @jperkin's work to get the M0+ working (let alone RISC-V!). The biggest challenge with the F2 honestly may be that they are hard to come by! If you have an evaluation board that you end up using, please point us to it so we can obtain one and help debug any issues you might have! |
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The STM32F1/2 series are fairly conventional M3 cores. While the MPU on the M3 is technically optional, both include it (and it's incredibly rare in practice to find an M3 without an MPU -- I think I've encountered one in the past 11 years?). @bcantrill is right that the main challenge would be the difference in register set size, which affects the context save/swap routines -- and also the debugger. I haven't used an M3 in a while, and Oxide isn't currently putting M3s in anything, so we're not actively pursuing a port. However, we are interested in an M0+ port, and since the M0+ has the same (user-mode) register set as the M3, getting that working would cover most of the moving pieces you'd need for M3 support. So, it's possible that an M3 port would become easier in the next few months. |
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@cbiffle can certainly answer with more authority, but it shouldn't be too bad -- this is a Cortex-M3, broadly similar to an M4. That said, that it is missing an FPU will surely necessitate some code changes -- for example (speaking from a Humility perspective), stack backtraces (via
humility tasks
won't work without some (modest) modification.So: very doable, but will require a modest amount of low-level work -- and should be much easier than @jperkin's work to get the M0+ working (let alone RISC-V!). The biggest challenge with the F2 honestly may be that they are hard to come by! If you have an evaluation board that you end up using, please point us to it so we can obtain one and help …