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SDN_mininet
SDN_mininet PublicThis is a repository for SDN-based implementation of MPLS network with OVS and OpenFlow, and Network Virtualization using OpenDayLight controller for remote approaches
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Multicycle_RISCV
Multicycle_RISCV PublicImplementation of a multi-cycle RISC-V processor for executing a RISC-V assembly code
Verilog 2
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Full_Bridge_Inverter
Full_Bridge_Inverter PublicPCB document of a 2-layer Full Bridge Inverter using IR2113 and IR2110 ICs
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xv6_OS_Project
xv6_OS_Project PublicCreating a Scheduler and several different Syscalls on xv6 OS
C
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ONT_SysVerilog
ONT_SysVerilog PublicSoftware-Based Optical Network SDH traffic generator written in SystemVerilog
SystemVerilog
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