Tile configuration addition pass #90
rengolintpp-benchmark.yml
on: pull_request
Check_LLVM
/
TPP-MLIR-LLVM-Base
8s
Check_LLVM
/
TPP-MLIR-LLVM-CUDA
7s
Check_LLVM
/
TPP-MLIR-LLVM-Vulkan
8s
TPP-MLIR-SPR-BASE
2m 33s
TPP-MLIR-SPR-OMP
5m 16s
TPP-MLIR-ZEN-BASE
0s
TPP-MLIR-ZEN-OMP
0s
TPP-MLIR-CLX-BASE
0s
TPP-MLIR-CLX-OMP
0s
TPP-MLIR-ADL-BASE
0s
TPP-MLIR-ADL-OMP
0s