Unified-Inclusive-L2-Cache-Controller-Simulation

Simulated operation of a cache controller in C++. It mimics operations performed by a real cache controller like returning data to higher level cache, updating state of a line and line evictions etc. It takes a memory trace file as input which contains read, write requests from higher level cache and snooped result on FSB. As a output displayed cache hit ratio, number of cache reads and writes. Designed cache has a total capacity of 8MB, uses 64-byte lines, 16 way set associative and implements write allocate policy. Pseudo LRU replacement is used for cache line evictions and MESIF protocol to maintain cache coherence with 3 other processors in shared memory configuration.