frontend: Add ND-front-ends for both 32 and 64-bit systems (#30, #32, #…

…33)

* MARIO: Generate ND frontends automatically

* PULP: Modify PULP wrapper to fit the 3D version #33

* PULP: Add a synthesis wrapper for DMAC Wrap #30

* PULP: Closed PR #32

* frontend: Cleanup and homogenization of the register interfaces, remove legacy drivers

---------

Co-authored-by: Tobias Senti <tsenti@ethz.ch>

Co-authored-by: Simone Di Stasi <simone.distasi@studio.unibo.it>

Co-authored-by: Alessandro Nadalini <alessandro.nadalini3@unibo.it>

.github/verible.waiver

@@ -6,7 +6,7 @@
 # - Thomas Benz <tbenz@iis.ee.ethz.ch>
 
 # Fix this ...
-waive --rule=line-length --location="src/frontends/desc64/idma_desc64.sv"
+waive --rule=line-length --location="src/frontend/desc64/idma_desc64.sv"
 
 # Declare zero-based big-endian unpacked dimensions sized as [N] -> legacy PULP code :S
 waive --rule=unpacked-dimensions-range-ordering --location="src/systems/pulpopen/dmac_wrap.sv"

.github/workflows/lint.yml

@@ -28,7 +28,6 @@ jobs:
           SPDX-License-Identifier: (SHL-0.51|Apache-2.0)
         # Exclude generated headers (no license checker support for optional lines)
         exclude_paths: |
-          src/systems/cva6_reg/driver/*.h
           target/sim/vsim/wave/tpl/*.do.tpl
 
   lint-sv:
@@ -69,7 +68,6 @@ jobs:
           AllowShortIfStatementsOnASingleLine: true,
           AllowShortLoopsOnASingleLine: true
           }
-        exclude_paths: src/systems/cva6_reg/driver/*.h target/sim/vsim/wave/tpl/*.tpl
 
   lint-python:
     runs-on: ubuntu-latest

Bender.local

@@ -1,2 +1,2 @@
 overrides:
-  axi: { git: "https://github.com/pulp-platform/axi.git", version: 0.39.0 }
+  axi: { git: "https://github.com/pulp-platform/axi.git", version: 0.39.1 }

Bender.yml

@@ -50,53 +50,39 @@ sources:
   - target: rtl
     files:
       # Level 0
-      - src/midends/idma_nd_midend.sv
+      - src/midend/idma_nd_midend.sv
 
   # Frontends (without inst64)
   - target: rtl
     files:
       # Level 0
-      - src/frontends/desc64/idma_desc64_shared_counter.sv
-      - src/frontends/idma_transfer_id_gen.sv
+      - src/frontend/desc64/idma_desc64_shared_counter.sv
+      - src/frontend/idma_transfer_id_gen.sv
       # Level 1
-      - src/frontends/reg32_2d/idma_reg32_2d.sv
-      - src/frontends/reg64/idma_reg64.sv
-      - src/frontends/reg64_2d/idma_reg64_2d.sv
-      - src/frontends/desc64/idma_desc64_reg_wrapper.sv
+      - src/frontend/desc64/idma_desc64_reg_wrapper.sv
       # Level 2
-      - src/frontends/desc64/idma_desc64.sv
+      - src/frontend/desc64/idma_desc64.sv
 
 
   # Synthesis wrappers
   - target: synth
     files:
       # Level 0
-      - src/frontends/desc64/idma_desc64_synth_pkg.sv
+      - src/frontend/desc64/idma_desc64_synth_pkg.sv
       - src/synth/idma_nd_backend_synth.sv
       # Level 1
-      - src/frontends/desc64/idma_desc64_synth.sv
+      - src/frontend/desc64/idma_desc64_synth.sv
 
   # Testbenches
   - target: test
     files:
       # Level 0
       - test/tb_idma_improved_fifo.sv
       - test/tb_idma_nd_backend.sv
-      - test/frontends/tb_idma_desc64.sv
+      - test/frontend/tb_idma_desc64.sv
       - test/future/idma_tb_per2axi.sv
       - test/future/idma_obi_asserter.sv
       - test/future/TLToAXI4.v
       # Level 1
       - test/future/idma_obi2axi_bridge.sv
       - test/future/idma_tilelink2axi_bridge.sv
-
-# Not yet..
-#  # Systems
-#  - target: all(pulp, not(mchan))
-#    files:
-#      - src/systems/pulpopen/dmac_wrap.sv
-#      - src/systems/pulpopen/synth_dmac_wrap.sv
-#
-#  - target: cva6
-#    files:
-#      - src/systems/cva6_reg/dma_core_wrap.sv

README.md

@@ -11,8 +11,9 @@ and in the [PULP Cluster](https://github.com/pulp-platform/pulp).
 iDMA currently implements the following protocols:
 - [AXI4](https://developer.arm.com/documentation/ihi0022/hc/?lang=en)[+ATOPs from AXI5](https://github.com/pulp-platform/axi)
 - [AXI4 Lite](https://developer.arm.com/documentation/ihi0022/hc/?lang=en)
+- [AXI4 Stream](https://developer.arm.com/documentation/ihi0051/b/?lang=en)
 - [OBI v1.5.0](https://github.com/openhwgroup/programs/blob/master/TGs/cores-task-group/obi/OBI-v1.5.0.pdf)
-
+- [TileLink UH v1.8.1](https://starfivetech.com/uploads/tilelink_spec_1.8.1.pdf)
 
 ## Modular Architecture
 iDMA is centered around the idea to split the DMA engine in 3 distinct parts:
@@ -27,7 +28,6 @@ new capabilities.
 
 ## Documentation
 The [latest documentation](https://pulp-platform.github.io/iDMA) can be accessed pre-built.
-The [Morty docs](https://pulp-platform.github.io/iDMA/morty/index.html) provide the generated description of the SystemVerilog files within this repository.
 
 ## Publications
 If you use iDMA in your work or research, you can cite us:
@@ -282,33 +282,31 @@ We currently do not include any free and open-source simulation setup. However,
 a simulation can be launched using:
 
 ```bash
-make gen_rtl_axi.obi.split
-make prepare_sim
-export VSIM="questa-2022.3 vsim"
-$VSIM -c -do "source scripts/compile_vsim.tcl; quit"
+make idma_sim_all
+cd target/sim/vsim
+$VSIM -c -do "source compile.tcl; quit"
 $VSIM -c -t 1ps -voptargs=+acc \
-     +job_file=jobs/multiprotocol/man_mixed.txt \
-     -logfile logs/multiprotocol.simple.vsim.log \
-     -wlf logs/multiprotocol.simple.wlf \
-     tb_idma_backend_r_axi_w_obi \
-     -do "source scripts/start_vsim.tcl; run -all"
+     +job_file=jobs/backend_rw_axi/simple.txt \
+     -logfile rw_axi_simple.log \
+     -wlf rw_axi_simple.wlf \
+     tb_idma_backend_rw_axi \
+     -do "source start.tcl; run -all"
 ```
 with gui:
 ```bash
-make gen_rtl_axi-tilelink.axi.split
-make prepare_sim
-export VSIM="questa-2022.3 vsim"
-$VSIM -c -do "source scripts/compile_vsim.tcl; quit"
+make idma_sim_all
+cd target/sim/vsim
+$VSIM -c -do "source compile.tcl; quit"
 $VSIM -t 1ps -voptargs=+acc \
-     +job_file=jobs/backend/man_tiny.txt \
-     -logfile logs/backend.simple.vsim.log \
-     -wlf logs/backend.medium.wlf \
-     tb_idma_backend_rw_axi_r_tilelink \
-     -do "source scripts/start_vsim.tcl; source scripts/waves/vsim_backend_rw_axi_r_tilelink.do; run -all"
+     +job_file=jobs/backend_rw_axi/simple.txt \
+     -logfile rw_axi_simple.log \
+     -wlf rw_axi_simple.wlf \
+     tb_idma_backend_rw_axi \
+     -do "source start.tcl; source wave/backend_rw_axi.do; run -all"
 ```
 
 Where:
-- `+job_file=jobs/backend/man_simple.txt` can point to any valid [job file](jobs/README.md)
-- `-logfile logs/backend.simple.vsim.log` denotes the log file
-- `-wlf logs/backend.simple.wlf` specifies a wave file
-- `tb_idma_backend` can be any of the supplied testbenches \(`test/tb_idma_*`\)
+- `job_file=jobs/backend_rw_axi/simple.txt` can point to any valid [job file](jobs/README.md)
+- `-logfile rw_axi_simple.log` denotes the log file
+- `-wlf rw_axi_simple.wlf` specifies a wave file
+- `tb_idma_backend_rw_axi` can be any of the supplied testbenches

doc/src/index.rst

@@ -43,17 +43,22 @@ The morty docs provide the generated description of the SystemVerilog files with
 
 .. only:: html
 
-  `R_AXI_W_OBI <idma_backend_r_axi_w_obi/index.html>`_
+  `R_AXI_W_OBI Backend <idma_backend_synth_r_axi_w_obi/index.html>`_
 
-  `R_OBI_W_AXI <idma_backend_r_obi_w_axi/index.html>`_
+  `R_OBI_W_AXI Backend <idma_backend_synth_r_obi_w_axi/index.html>`_
 
-  `RW_AXI <idma_backend_rw_axi/index.html>`_
+  `RW_AXI Backend <idma_backend_synth_rw_axi/index.html>`_
 
-.. image:: ../fig/graph/idma_backend_r_axi_w_obi.png
+  `ND Backend <idma_nd_backend_synth/index.html>`_
+
+.. image:: ../fig/graph/idma_backend_synth_r_axi_w_obi.png
+  :width: 600
+
+.. image:: ../fig/graph/idma_backend_synth_r_obi_w_axi.png
   :width: 600
 
-.. image:: ../fig/graph/idma_backend_r_obi_w_axi.png
+.. image:: ../fig/graph/idma_backend_synth_rw_axi.png
   :width: 600
 
-.. image:: ../fig/graph/idma_backend_rw_axi.png
-  :width: 600
+.. image:: ../fig/graph/idma_nd_backend_synth.png
+  :width: 600

idma.mk

@@ -19,6 +19,9 @@ VLOGAN      ?= vlogan
 # iDMA Variants
 IDMA_BACKEND_IDS ?= rw_axi r_obi_w_axi r_axi_w_obi
 
+# generated frontends
+IDMA_FE_IDS ?= reg32_3d reg64_2d
+
 # iDMA paths
 IDMA_ROOT     ?= $(shell $(BENDER) path idma)
 IDMA_REG_DIR  := $(shell $(BENDER) path register_interface)
@@ -46,32 +49,6 @@ IDMA_RELATIVE_PATH_REGEX := 's/$(IDMA_PATH_ESCAPED)/./'
 .DELETE_ON_ERROR:
 
 
-# --------------
-# Help
-# --------------
-
-.PHONY: idma_all idma_help
-
-idma_all: idma_help
-
-idma_help:
-	@echo ""
-	@echo "iDMA Makefile"
-	@echo "-------------"
-	@echo ""
-	@echo "prepare_sim:                       uses bender to generate the analyze scripts needed for simulating the iDMA"
-	@echo "bin/iDMA.vcs VCS_TP=**YOUR_TB**:   creates the VCS executable"
-	@echo "obj_iDMA VLT_TOP=**YOUR_TOP_LVL**: elaborates the hardware using verilator"
-	@echo "pickle:                            uses morty to generate a pickled version of the hardware"
-	@echo "doc:                               generates the documentation in doc/build"
-	@echo "gen_ci:                            regenerates the gitlab CI (only ETH internal used)"
-	@echo "gen_regs:                          regenerates the registers using reggen"
-	@echo ""
-	@echo "clean:                             cleans generated files"
-	@echo "nuke:                              cleans all generated file, also almost all files checked in"
-	@echo ""
-
-
 # --------------
 # RTL
 # --------------
@@ -108,29 +85,29 @@ IDMA_RTL_FILES  := $(IDMA_RTL_DIR)/idma_transport_layer \
 IDMA_VSIM_DIR   := $(IDMA_ROOT)/target/sim/vsim
 
 define idma_gen
-	$(PYTHON) $(IDMA_GEN) --entity $1 --tpl $2 --db $3 --ids $4 > $5
+	$(PYTHON) $(IDMA_GEN) --entity $1 --tpl $2 --db $3 --ids $4 --fids $5 > $6
 endef
 
 $(IDMA_GEN_BENDER): $(IDMA_GEN) $(IDMA_GEN_SRC) $(IDMA_RTL_DIR)/tpl/Bender.yml.tpl $(IDMA_DB_FILES) $(IDMA_ROOT)/idma.mk
-	  $(call idma_gen,bender,$(IDMA_RTL_DIR)/tpl/Bender.yml.tpl,$(IDMA_DB_FILES),$(IDMA_BACKEND_IDS),$@)
+	$(call idma_gen,bender,$(IDMA_RTL_DIR)/tpl/Bender.yml.tpl,$(IDMA_DB_FILES),$(IDMA_BACKEND_IDS),$(IDMA_FE_IDS),$@)
 
 $(IDMA_RTL_DIR)/idma_transport_layer_%.sv: $(IDMA_GEN) $(IDMA_GEN_BENDER) $(IDMA_ROOT)/src/backend/tpl/idma_transport_layer.sv.tpl
-	$(call idma_gen,transport,$(IDMA_ROOT)/src/backend/tpl/idma_transport_layer.sv.tpl,$(IDMA_DB_FILES),$*,$@)
+	$(call idma_gen,transport,$(IDMA_ROOT)/src/backend/tpl/idma_transport_layer.sv.tpl,$(IDMA_DB_FILES),$*,,$@)
 
 $(IDMA_RTL_DIR)/idma_legalizer_%.sv: $(IDMA_GEN) $(IDMA_GEN_BENDER) $(IDMA_ROOT)/src/backend/tpl/idma_legalizer.sv.tpl
-	$(call idma_gen,legalizer,$(IDMA_ROOT)/src/backend/tpl/idma_legalizer.sv.tpl,$(IDMA_DB_FILES),$*,$@)
+	$(call idma_gen,legalizer,$(IDMA_ROOT)/src/backend/tpl/idma_legalizer.sv.tpl,$(IDMA_DB_FILES),$*,,$@)
 
 $(IDMA_RTL_DIR)/idma_backend_%.sv: $(IDMA_GEN) $(IDMA_RTL_DIR)/idma_legalizer_%.sv $(IDMA_RTL_DIR)/idma_transport_layer_%.sv $(IDMA_ROOT)/src/backend/tpl/idma_backend.sv.tpl
-	$(call idma_gen,backend,$(IDMA_ROOT)/src/backend/tpl/idma_backend.sv.tpl,$(IDMA_DB_FILES),$*,$@)
+	$(call idma_gen,backend,$(IDMA_ROOT)/src/backend/tpl/idma_backend.sv.tpl,$(IDMA_DB_FILES),$*,,$@)
 
 $(IDMA_RTL_DIR)/idma_backend_synth_%.sv: $(IDMA_GEN) $(IDMA_RTL_DIR)/idma_backend_%.sv $(IDMA_ROOT)/src/backend/tpl/idma_backend_synth.sv.tpl
-	$(call idma_gen,synth_wrapper,$(IDMA_ROOT)/src/backend/tpl/idma_backend_synth.sv.tpl,$(IDMA_DB_FILES),$*,$@)
+	$(call idma_gen,synth_wrapper,$(IDMA_ROOT)/src/backend/tpl/idma_backend_synth.sv.tpl,$(IDMA_DB_FILES),$*,,$@)
 
 $(IDMA_RTL_DIR)/tb_idma_backend_%.sv: $(IDMA_GEN) $(IDMA_RTL_DIR)/idma_backend_%.sv $(IDMA_ROOT)/test/tpl/tb_idma_backend.sv.tpl
-	$(call idma_gen,testbench,$(IDMA_ROOT)/test/tpl/tb_idma_backend.sv.tpl,$(IDMA_DB_FILES),$*,$@)
+	$(call idma_gen,testbench,$(IDMA_ROOT)/test/tpl/tb_idma_backend.sv.tpl,$(IDMA_DB_FILES),$*,,$@)
 
 $(IDMA_VSIM_DIR)/wave/backend_%.do: $(IDMA_GEN) $(IDMA_RTL_DIR)/tb_idma_backend_%.sv $(IDMA_VSIM_DIR)/wave/tpl/backend.do.tpl
-	$(call idma_gen,vsim_wave,$(IDMA_VSIM_DIR)/wave/tpl/backend.do.tpl,$(IDMA_DB_FILES),$*,$@)
+	$(call idma_gen,vsim_wave,$(IDMA_VSIM_DIR)/wave/tpl/backend.do.tpl,$(IDMA_DB_FILES),$*,,$@)
 
 idma_rtl_clean:
 	rm -f $(IDMA_RTL_DIR)/Bender.yml
@@ -153,30 +130,54 @@ IDMA_DOC_SRC_DIR := $(IDMA_ROOT)/doc/src
 IDMA_DOC_FIG_DIR := $(IDMA_ROOT)/doc/fig
 IDMA_DOC_OUT_DIR := $(IDMA_ROOT)/target/doc
 IDMA_HTML_DIR    := $(IDMA_DOC_OUT_DIR)/html
-IDMA_FE_DIR      := $(IDMA_ROOT)/src/frontends
-IDMA_FE_REGS     := desc64 reg32_2d reg64 reg64_2d
+IDMA_FE_DIR      := $(IDMA_ROOT)/src/frontend
+IDMA_FE_REGS     := desc64
+IDMA_FE_REGS     += $(IDMA_FE_IDS)
+
+# customize the HJSON
+$(IDMA_RTL_DIR)/idma_%.hjson: $(IDMA_GEN) $(IDMA_FE_DIR)/reg/tpl/idma_reg.hjson.tpl $(IDMA_GEN_BENDER)
+	$(call idma_gen,reg_hjson,$(IDMA_FE_DIR)/reg/tpl/idma_reg.hjson.tpl,,,$*,$@)
+
+IDMA_REG_CUST_ALL += $(foreach Y,$(IDMA_FE_IDS),$(IDMA_RTL_DIR)/idma_$Y.hjson)
+
+# ----
 
 $(IDMA_HTML_DIR)/regs/reg_html.css:
 	mkdir -p $(IDMA_HTML_DIR)/regs
 	cp $(IDMA_REG_DIR)/vendor/lowrisc_opentitan/util/reggen/reg_html.css $@
 
-$(IDMA_RTL_DIR)/idma_%_reg_pkg.sv $(IDMA_RTL_DIR)/idma_%_reg_top.sv: $(IDMA_GEN_BENDER)
-	$(PYTHON) $(IDMA_REGTOOL) $(IDMA_FE_DIR)/$*/idma_$*.hjson -t $(IDMA_RTL_DIR) -r
-
-$(IDMA_HTML_DIR)/regs/idma_%.html: $(IDMA_HTML_DIR)/regs/reg_html.css
-	$(PRINTF) "<!DOCTYPE html>\n<html>\n<head>\n<link rel="stylesheet" href="reg_html.css">\n</head>\n" > $@
-	$(PYTHON) $(IDMA_REGTOOL) $(IDMA_FE_DIR)/$*/idma_$*.hjson -d >> $@
-	$(PRINTF) "</html>\n" >> $@
+$(IDMA_RTL_DIR)/idma_%_reg_pkg.sv $(IDMA_RTL_DIR)/idma_%_reg_top.sv: $(IDMA_GEN_BENDER) $(IDMA_REG_CUST_ALL)
+	if [ -a "$(IDMA_FE_DIR)/$*/idma_$*.hjson" ]; then \
+	    $(PYTHON) $(IDMA_REGTOOL) $(IDMA_FE_DIR)/$*/idma_$*.hjson -t $(IDMA_RTL_DIR) -r; \
+	else \
+	    $(PYTHON) $(IDMA_REGTOOL) $(IDMA_RTL_DIR)/idma_$*.hjson -t $(IDMA_RTL_DIR) -r; \
+	fi
+
+$(IDMA_RTL_DIR)/idma_%_top.sv: $(IDMA_GEN) $(IDMA_FE_DIR)/reg/tpl/idma_reg.sv.tpl $(IDMA_GEN_BENDER)
+	$(call idma_gen,reg_top,$(IDMA_FE_DIR)/reg/tpl/idma_reg.sv.tpl,,,$*,$@)
+
+$(IDMA_HTML_DIR)/regs/idma_%.html: $(IDMA_HTML_DIR)/regs/reg_html.css $(IDMA_REG_CUST_ALL)
+	if [ -a "$(IDMA_FE_DIR)/$*/idma_$*.hjson" ]; then \
+		$(PRINTF) "<!DOCTYPE html>\n<html>\n<head>\n<link rel="stylesheet" href="reg_html.css">\n</head>\n" > $@; \
+		$(PYTHON) $(IDMA_REGTOOL) $(IDMA_FE_DIR)/$*/idma_$*.hjson -d >> $@; \
+		$(PRINTF) "</html>\n" >> $@; \
+	else \
+		$(PRINTF) "<!DOCTYPE html>\n<html>\n<head>\n<link rel="stylesheet" href="reg_html.css">\n</head>\n" > $@; \
+		$(PYTHON) $(IDMA_REGTOOL) $(IDMA_RTL_DIR)/idma_$*.hjson -d >> $@; \
+		$(PRINTF) "</html>\n" >> $@; \
+	fi
 
 idma_reg_clean:
 	rm -rf $(IDMA_HTML_DIR)/regs
 	rm -f  $(IDMA_RTL_DIR)/*_reg_top.sv
 	rm -f  $(IDMA_RTL_DIR)/*_reg_pkg.sv
 	rm -f  $(IDMA_RTL_DIR)/Bender.yml
+	rm -f  $(IDMA_REG_CUST_ALL)
 
 # assemble the required files
 IDMA_RTL_ALL     += $(foreach Y,$(IDMA_FE_REGS),$(IDMA_RTL_DIR)/idma_$Y_reg_pkg.sv)
 IDMA_RTL_ALL     += $(foreach Y,$(IDMA_FE_REGS),$(IDMA_RTL_DIR)/idma_$Y_reg_top.sv)
+IDMA_RTL_ALL     += $(foreach Y,$(IDMA_FE_REGS),$(IDMA_RTL_DIR)/idma_$Y_top.sv)
 IDMA_RTL_DOC_ALL += $(foreach Y,$(IDMA_FE_REGS),$(IDMA_HTML_DIR)/regs/idma_$Y.html)
 
 
@@ -193,7 +194,7 @@ $(IDMA_PICKLE_DIR)/sources.json: $(IDMA_BENDER_FILES) $(IDMA_TB_ALL) $(IDMA_RTL_
 	$(BENDER) update
 	$(BENDER) checkout
 	mkdir -p $(IDMA_PICKLE_DIR)
-	$(BENDER) sources -f -t rtl -t synthesis -t synth -t pulp -t asic | sed -e $(IDMA_RELATIVE_PATH_REGEX) > $@
+	$(BENDER) sources -f -t rtl -t synthesis -t synth -t asic | sed -e $(IDMA_RELATIVE_PATH_REGEX) > $@
 
 $(IDMA_PICKLE_DIR)/%.sv: $(IDMA_PICKLE_DIR)/sources.json
 	$(MORTY) -f $< -i --top $* $(IDMA_MORTY_ARGS) --propagate_defines -o $@
@@ -392,7 +393,7 @@ idma_nuke: idma_clean idma_nonfree_clean
 # Phony Targets
 # --------------
 
-.PHONY: idma_doc_all idma_pickle_all idma_rtl_all idma_sim_all
+.PHONY: idma_all idma_doc_all idma_pickle_all idma_rtl_all idma_sim_all
 
 idma_doc_all: idma_spinx_doc
 
@@ -401,3 +402,5 @@ idma_pickle_all: $(IDMA_PICKLE_ALL)
 idma_hw_all: $(IDMA_RTL_ALL)
 
 idma_sim_all: $(IDMA_VCS_DIR)/compile.sh $(IDMA_VSIM_DIR)/compile.tcl
+
+idma_all: idma_hw_all idma_sim_all idma_doc_all idma_pickle_all

jobs/jobs.json

@@ -106,8 +106,8 @@
     },
     "4d_extension" : {
         "jobs" : {
-            "simple"          : "4d_extension/simple.txt",
-            "linear_2d"       : "4d_extension/linear_2D.txt"
+            "simple"    : "4d_extension/simple.txt",
+            "linear_2d" : "4d_extension/linear_2D.txt"
         },
         "params" : {
             "DataWidth"           : 32,

src/frontends/idma_transfer_id_gen.sv → src/frontend/idma_transfer_id_gen.sv

@@ -1,11 +1,10 @@
-// Copyright 2022 ETH Zurich and University of Bologna.
+// Copyright 2023 ETH Zurich and University of Bologna.
 // Solderpad Hardware License, Version 0.51, see LICENSE for details.
 // SPDX-License-Identifier: SHL-0.51
 
 // Authors:
 // - Thomas Benz <tbenz@ethz.ch>
 
-
 /// DMA transaction id generator. Increases the transaction id on every request.
 module idma_transfer_id_gen #(
     parameter int unsigned  IdWidth = -1