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desc64: Update synth module for descriptor frontend
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Now that we changed the frontend, we also need to update its
synth module.
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Axel Vanoni committed Aug 15, 2022
1 parent b41b8be commit a85fbbe
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Showing 2 changed files with 73 additions and 55 deletions.
92 changes: 57 additions & 35 deletions src/frontends/desc64/idma_desc64_synth.sv
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// synth wrapper
module idma_desc64_synth #(
parameter int unsigned AddrWidth = idma_desc64_synth_pkg::AddrWidth,
parameter type burst_req_t = idma_desc64_synth_pkg::burst_req_t,
parameter type reg_rsp_t = idma_desc64_synth_pkg::reg_rsp_t,
parameter type reg_req_t = idma_desc64_synth_pkg::reg_req_t
parameter int unsigned AddrWidth = idma_desc64_synth_pkg::AddrWidth,
parameter int unsigned DataWidth = idma_desc64_synth_pkg::DataWidth,
parameter int unsigned AxiIdWidth = idma_desc64_synth_pkg::IdWidth,
parameter type idma_req_t = idma_desc64_synth_pkg::idma_req_t,
parameter type idma_rsp_t = idma_desc64_synth_pkg::idma_rsp_t,
parameter type axi_rsp_t = idma_desc64_synth_pkg::axi_rsp_t,
parameter type axi_req_t = idma_desc64_synth_pkg::axi_req_t,
parameter type reg_rsp_t = idma_desc64_synth_pkg::reg_rsp_t,
parameter type reg_req_t = idma_desc64_synth_pkg::reg_req_t,
parameter int unsigned InputFifoDepth = idma_desc64_synth_pkg::InputFifoDepth,
parameter int unsigned PendingFifoDepth = idma_desc64_synth_pkg::PendingFifoDepth
)(
input logic clk_i,
input logic rst_ni,
output reg_req_t master_req_o,
input reg_rsp_t master_rsp_i,
input reg_req_t slave_req_i,
output reg_rsp_t slave_rsp_o,
output burst_req_t dma_be_req_o,
output logic dma_be_valid_o,
input logic dma_be_ready_i,
input logic dma_be_tx_complete_i,
input logic dma_be_idle_i,
output logic irq_o
input logic clk_i ,
input logic rst_ni ,
output axi_req_t master_req_o ,
input axi_rsp_t master_rsp_i ,
input logic [AxiIdWidth-1:0] axi_r_id_i ,
input logic [AxiIdWidth-1:0] axi_w_id_i ,
input reg_req_t slave_req_i ,
output reg_rsp_t slave_rsp_o ,
output idma_req_t dma_be_req_o ,
output logic dma_be_req_valid_o,
input logic dma_be_req_ready_i,
input idma_rsp_t dma_be_rsp_i ,
input logic dma_be_rsp_valid_i,
output logic dma_be_rsp_ready_o,
input logic dma_be_idle_i ,
output logic irq_o
);

idma_desc64_top #(
.AddrWidth ( AddrWidth ),
.burst_req_t ( burst_req_t ),
.reg_rsp_t ( reg_rsp_t ),
.reg_req_t ( reg_req_t )
) i_idma_desc64 (
.clk_i,
.rst_ni,
.master_req_o,
.master_rsp_i,
.slave_req_i,
.slave_rsp_o,
.dma_be_req_o,
.dma_be_valid_o,
.dma_be_ready_i,
.dma_be_tx_complete_i,
.dma_be_idle_i,
.irq_o
);
idma_desc64_top #(
.AddrWidth,
.DataWidth,
.AxiIdWidth,
.idma_req_t,
.idma_rsp_t,
.axi_req_t,
.axi_rsp_t,
.reg_req_t,
.reg_rsp_t,
.InputFifoDepth,
.PendingFifoDepth
) i_dma_desc64 (
.clk_i ,
.rst_ni ,
.master_req_o ,
.master_rsp_i ,
.axi_r_id_i ,
.axi_w_id_i ,
.slave_req_i ,
.slave_rsp_o ,
.dma_be_req_o ,
.dma_be_req_valid_o,
.dma_be_req_ready_i,
.dma_be_rsp_i ,
.dma_be_rsp_valid_i,
.dma_be_rsp_ready_o,
.dma_be_idle_i ,
.irq_o
);

endmodule : idma_desc64_synth
36 changes: 16 additions & 20 deletions src/frontends/desc64/idma_desc64_synth_pkg.sv
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package idma_desc64_synth_pkg;

`include "register_interface/typedef.svh"

localparam int unsigned AddrWidth = 64;
localparam int unsigned DataWidth = 64;
localparam int unsigned StrbWidth = DataWidth / 8;
localparam int unsigned OneDLength = 32;
localparam int unsigned IdWidth = 8;
`include "idma/typedef.svh"

localparam int unsigned AddrWidth = 64;
localparam int unsigned DataWidth = 64;
localparam int unsigned StrbWidth = DataWidth / 8;
localparam int unsigned OneDLength = 32;
localparam int unsigned IdWidth = 8;
localparam int unsigned UserWidth = 1;
localparam int unsigned TFLenWidth = 32;
localparam int unsigned InputFifoDepth = 8;
localparam int unsigned PendingFifoDepth = 8;

typedef logic [AddrWidth-1:0] addr_t;
typedef logic [DataWidth-1:0] data_t;
typedef logic [StrbWidth-1:0] strb_t;
typedef logic [OneDLength-1:0] length_t;
typedef logic [IdWidth-1:0] id_t;
typedef logic [UserWidth-1:0] user_t;
typedef logic [TFLenWidth-1:0] tf_len_t;

`REG_BUS_TYPEDEF_ALL(reg, addr_t, data_t, strb_t)

typedef struct packed {
id_t id;
addr_t src;
addr_t dst;
length_t num_bytes;
axi_pkg::cache_t src_cache;
axi_pkg::cache_t dst_cache;
axi_pkg::burst_t src_burst;
axi_pkg::burst_t dst_burst;
logic decouple_rw;
logic deburst;
logic serialize;
} burst_req_t;
`AXI_TYPEDEF_ALL(axi, addr_t, id_t, data_t, strb_t, user_t)
`IDMA_TYPEDEF_FULL_REQ_T(idma_req_t, id_t, addr_t, tf_len_t)
`IDMA_TYPEDEF_FULL_RSP_T(idma_rsp_t, addr_t)

endpackage : idma_desc64_synth_pkg

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