fpga: Adapted flow to new directory

Bender.yml

@@ -38,6 +38,7 @@ workspace:
 
 export_include_dirs:
   - hw/spm_interface/include
+  - hw/occamy
 
 sources:
   # future
@@ -46,6 +47,7 @@ sources:
   # snitch_read_only_cache
   - hw/snitch_read_only_cache/src/snitch_axi_to_cache.sv
   - hw/snitch_read_only_cache/src/snitch_read_only_cache.sv
+
   - target: test
     files:
       - hw/snitch_read_only_cache/test/snitch_read_only_cache_tb.sv

target/fpga/Makefile

@@ -13,6 +13,8 @@ EXT_JTAG    ?= 0
 VCU         ?= 01
 FPGA_ID     := 091847100576A
 HW_SERVER   := bordcomputer:3231
+BENDER      ?= bender
+VIVADO      ?= vitis-2020.2 vivado
 
 # Select VCU128-02
 ifeq ($(VCU),02)
@@ -34,8 +36,6 @@ DTB = bootrom/occamy.dtb
 default: all
 all: occamy_vcu128
 
-include $(ROOT)/util/Makefrag
-
 vivado_ips/occamy_xilinx:
 	${MAKE} -C vivado_ips occamy_xilinx
 
@@ -46,7 +46,7 @@ occamy_vcu128: vivado_ips/occamy_xilinx bootrom/bootrom-spl.coe define_defines_i
 	${VIVADO} -mode batch -source occamy_vcu128.tcl -tclargs $(DEBUG) $(EXT_JTAG) $(NPROC) ${MKFILE_DIR}/bootrom/bootrom-spl.coe
 
 define_defines_includes_no_simset.tcl: $(BENDER_FILES)
-	${BENDER} script vivado -t cv64a6_imafdc_sv39 --only-defines --only-includes --no-simset > $@
+	${BENDER} script vivado -t occamy -t cv64a6_imafdc_sv39 --only-defines --only-includes --no-simset > $@
 
 program:
 	${VIVADO} -mode batch -source occamy_vcu128_program.tcl -tclargs ${VCU}

target/fpga/bootrom/Makefile

@@ -8,8 +8,6 @@ MKFILE_PATH := $(abspath $(lastword $(MAKEFILE_LIST)))
 MKFILE_DIR  := $(dir $(MKFILE_PATH))
 ROOT        := ${MKFILE_DIR}../../../../..
 
-include $(ROOT)/util/Makefrag
-
 CVA6_SDK  ?= $(ROOT)/../cva6-sdk
 UBOOT_SPL_BIN ?= $(CVA6_SDK)/u-boot/spl/u-boot-spl.bin
 
@@ -28,7 +26,7 @@ CFLAGS 	= -Os -g -Werror -ffreestanding -fno-strict-aliasing
 CFLAGS += -static -nostartfiles -nostartfiles
 CFLAGS += -fno-omit-frame-pointer -fno-optimize-sibling-calls -fno-stack-protector
 CFLAGS += -mno-save-restore -mstrict-align
-CFLAGS += -mabi=lp64d -march=rv64imafd
+CFLAGS += -mabi=lp64d -march=rv64imafd_zifencei
 CFLAGS += -mcmodel=medany
 
 GIT_SHA := $(shell git describe --match=NeVeRmAtCh --always --abbrev=10 --dirty)
@@ -67,4 +65,4 @@ clean:
 %.tcl:  %.bin
 	@echo "TCL   <= $<"
 	@$(call BINRAY_SIZE_CHECK,$<,1000000)
-	@$(BIN2JTAG) -c32 -b 0 -d hw_axi_1 $< > $@
+	bin2jtag -c32 -b 0 -d hw_axi_1 $< > $@

target/fpga/vivado_ips/Makefile

@@ -9,18 +9,15 @@ MKFILE_DIR  := $(dir $(MKFILE_PATH))
 ROOT        := ${MKFILE_DIR}../../../../..
 DEBUG       ?= 0
 
-VIVADO ?= vivado
-BENDER ?= bender
+BENDER      ?= bender
+VIVADO      ?= vitis-2020.2 vivado
 
-BENDER_TARGETS += -t cv64a6_imafdc_sv39
+BENDER_TARGETS += -t cv64a6_imafdc_sv39 -t occamy
 ifeq ($(EXT_JTAG), 0)
 	BENDER_TARGETS += -t bscane
 endif
 
-include $(ROOT)/util/Makefrag
-
 occamy_xilinx: define-sources.tcl
-	$(MAKE) -C ../../ update-source
 	${VIVADO} -mode batch -source occamy_xilinx.tcl -tclargs $(DEBUG) $(EXT_JTAG)
 
 define-sources.tcl:

target/fpga/vivado_ips/occamy_xilinx.tcl

@@ -56,4 +56,4 @@ ipx::create_xgui_files [ipx::current_core]
 ipx::update_checksums [ipx::current_core]
 ipx::save_core [ipx::current_core]
 ipx::check_integrity [ipx::current_core]
-ipx::save_core [ipx::current_core]
+ipx::save_core [ipx::current_core]