Feature/iir tweaks #178
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Feature/iir tweaks #178
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* origin/master: Adding comment about checking for flag pass completion Adding comments about execution hanging to transfer complete waits Removing default parameter settings Updating DAC SPI structures to own HAL SPI structure for safety guarantees Moving constants to a new file Removing copy to DAC buffers, adding in-place borrow of output buffers Marking AXISRAM as NOLOAD Refactoring timer channels to macros, adding safety notes Adding DMA support for DAC writes Adding sampling_timer file Adding compile-time management of TIM2 channels Reverting changeset Adding documentation Reverting openocd change Adding updated docs for adc file Combining ADC + DAC ISRs Adding WIP updates Formatting Adding ADC/DAC modules Adding WIP updates to using DMA
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@ryan-summers could you review and give it a quick test on hardware (see whether it behaves as it did before passing through your 1 kHz test signal -> ADC -> DAC -> scope)? |
jordens
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@jordens Programming this branch onto a stabilizer with a 1KHz 1V amplitude sinusoid into ADC0 shows an identical sinusoid on DAC0 output. I don't see any distortion or inconsistencies introduced as a result of these changes. I also ran the |
ryan-summers
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Nov 30, 2020
* origin/master: more nightly clippy lints clippy lints gha: clippy-check build(deps): bump paste from 1.0.2 to 1.0.3 build(deps): bump panic-semihosting from 0.5.4 to 0.5.6
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bors r+ |
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Build succeeded: |
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Some minor IIR tweaks and a couple more relevant compiler flags.
Untested on hardware.