Add features to build a TyVcd with additional artifact scopes

[rameloni]

Sometimes simulation tools may create additional scopes in a testbench that wrap the dut. An example is ChiselSim for chisel which creates 2 additional scopes in the output trace file (TOP and svsimTestbench) in the testbench and instantiates the module as dut. On the other hand, firtool generates the hgldd file without that knowledge, therefore a tool should know how these additional scopes are linked to the hgldd.

To fix this, it should be possible to provide a function that, given a sequence of top_scope_names to be added and the top_module_name, produces a new Hgldd with update scopes, like the following:

fn add_extra_modules(
    hgldds: Vec<Hgldd>,         // source hgldd
    extra_modules: Vec<String>, // the top scopes to be added (i.e. TOP, svsimTb, dut)
    top_module_name: &String,   // the name of the current top_module
) -> Vec<Hgldd>

And it would generate a new Hgldd with the following hierarchy of scopes:
TOP -> svsmiTb -> dut -> others... and the dut replaces top_module_names.

To avoid the name replacement of the top module, one can specify that name as last entry of the list extra_modules. In this way the solution should cover 2 cases (allowing to replace or not the top module name).