RapidStream Cookbook offers a curated set of Python script templates and in-depth tutorials designed to guide you in optimizing your FPGA designs efficiently using RapidStream's Python-driven development flows.
RapidStream is a streamlined development flow for modern FPGAs, designed to help users quickly create high-performance systems. By working alongside FPGA vendor tools, RapidStream allows for the easy integration of small building blocks into complex, high-frequency designs. Users can take advantage of RapidStream's Python-based scripting language to efficiently implement high-performance FPGA accelerators using software-defined flows.
If you're new to RapidStream and want to learn the basics or get a quick overview of how it works, you may read rapidstream documents and check out the recipes in the Getting Started section. Once you're familiar with the fundamentals, explore real-world applications of RapidStream on various benchmarks in the Benchmarks section.
To get a local copy of the RapidStream Cookbook repository, clone it to your system by running the following command:
git clone https://github.com/rapidstream-org/rapidstream-cookbook.git
cd rapidstream-cookbookYou must have RapidStream installed from here with a valid RapidStream license, and a valid Vivado Design Suite license to download or run the cookbooks. If you are an academic researcher or would like to contribute to this cookbook, please contact us at https://rapidstream-da.com/ for a free RapidStream license.
We recommend using Vivado version 2023.2 or later. Source the Vivado settings script before running the RapidStream Python scripts. For example, to source the Vivado settings script, run the following command:
source <Vivado_installation_path>/Vivado/2023.2/settings64.shWe've created a Makefile for each recipe in this repository to help you get started quickly. Simply navigate to the specific example directory and run make to compile.
cd getting_started/mixed_sources
makeThe default branch always matches the latest RapidStream release. Please update your software before using the recipes.
| Begin your journey with RapidStream by integrating the flow into your FPGA vendor tool. No prior experience required – start from here! | ||
| Basic Usages | ||
| AMD Vitis Design | Mixed Sources Design | |
| Rapidstream TAPA Design | ||
| Custom Devices | ||
| Custom Vitis Platforms | Custom Vivado Parts | |
| Discover how RapidStream flow streamlines FPGA acceleration design of state-of-the-art architectures, enabling you to achieve optimal performance for performance-critical systems. | ||||
| Scientific Computation | ||||
| Design | Developer | Platforms | Sources | Purpose |
| Serpens | Song et al. (FPGA '22) |
Vitis U55C XDMA | TAPA HLS | Accelerator for general-purpose sparse-matrix dense-matrix multiplication. |
| Sextans | Song et al. (FPGA '22) |
Vitis U55C XDMA | TAPA HLS | Accelerator for general-purpose sparse-matrix dense-matrix multiplication. |
| Callipepla | Song et al. (FPGA '22) |
Vitis U55C XDMA | TAPA HLS | Accelerator for general-purpose sparse-matrix dense-matrix multiplication. |
| KNN Digit Recognition | Xiao et al. (FPL '22) |
Vitis U55C XDMA | TAPA HLS | K-Nearest Neighbours for Digit Recognition. |
| Bloom Filter | Simon Fraser University | Vitis U55C XDMA | TAPA HLS | Accelerator for Bloom Filter. |
| Stencil Application | Simon Fraser University | Vitis U55C XDMA | TAPA HLS | Accelerator for Stencil Application. |
| KNN | Simon Fraser University | Vitis U55C XDMA | TAPA HLS | Accelerator for K-Nearest-Neighbor. |
| ORC Decoder | Simon Fraser University | Vitis U55C XDMA | TAPA HLS | Accelerator for ORC Decoder. |
| Discover how RapidStream flow streamlines FPGA acceleration design of state-of-the-art architectures, enabling you to achieve optimal performance for performance-critical systems. | ||||
| Scientific Computation | ||||
| Design | Developer | Platforms | Sources | Purpose |
| CNN13x2 | AutoBridge | U50 U55c U280 U250 |
Vitis HLS | An HLS accelerator for the convolutional neural network kernel. |
| CNN13x{4..16} | AutoBridge | U250 | Vitis HLS | An HLS accelerator for the convolutional neural network kernel. |
| LLM | Chen et al. (TRETS) |
U50 U55c U280 U250 |
Vitis HLS | A model-specific spatial acceleration for Large Language Model (LLM) inference on FPGAs. |
| Discover how RapidStream flow streamlines FPGA acceleration design of state-of-the-art architectures, enabling you to achieve optimal performance for performance-critical systems. | ||||
| Scientific Computation | ||||
| Design | Developer | Platforms | Sources | Purpose |
| CNN | AutoBridge | RapidShell (U50) | Vitis HLS, Manual Verilog | An HLS accelerator for the convolutional neural network kernel. |
| LLM | Chen et al. (TRETS) |
VCK190 VHK158 VP1552 VU9P |
Vitis HLS, Manual Verilog | A model-specific spatial acceleration for Large Language Model (LLM) inference on FPGAs. |
| cnn13x2 | AutoBridge | RapidShell (U50) | Vitis HLS, Manual Verilog | Pure text Vivado source project for RTL developers. |
| PLD | Xiao et al. (ASPLOS '22) |
RapidShell (U50) | Vitis HLS, Manual Verilog | Pure text Vivado source project for RTL developers. |
- For questions about the RapidStream software, contact your sales representative.
- For questions or issues about the recipes, create an issue.
To get a free academic license of RapidStream for contributing to the cookbook or showcasing your FPGA design success story, simply reach out to us. Fork this repository, add your design or usage guide, and create a pull request. We'll gladly include your contribution and help increase your project's visibility.
All tests and pre-commit checks shall pass before committing to the repository.
Before making the first commit, install pre-commit for Git by running the following commands:
pip install pre-commit
pre-commit installYou may then run pre-commit to check if the formatting and linting are correct:
pre-commit runWe use Conventional Commits as our commit message guideline.
Visual Studio Code users could configure to use RapidStream as the Python interpreter, run:
which rapidstreamThen enter the output into the Command Palette (⇧⌘P on macOS, or Shift-Ctrl-P on other platforms): Python: Select Interpreter > Enter interpreter path.....
The RapidStream Cookbook is an open source project managed by RapidStream Design Automation, Inc., who is authorized by the contributors to license the software under the MIT license.
The repository includes some data files generated by the Vivado Design Suite that are copyrighted by Advanced Micro Devices (AMD), Inc. These files are provided for informational purposes only and are subject to AMD's licensing terms and conditions. The MIT open-source license of this repository does not apply to the these copyrighted files, and AMD's licensing terms and conditions solely govern the use of these copyrighted files. By accessing or using these copyrighted files in this repository, you acknowledge that you have a valid AMD Vivado license and agree to comply with all applicable licensing terms and conditions. The repository maintainers make no representations or warranties regarding these copyrighted files and shall not be held liable for any issues arising from their use. It is your responsibility to ensure compliance with AMD's licensing terms and conditions. For more information about AMD's licensing terms and conditions, please refer to the AMD website or contact AMD directly. By using this repository, you agree to indemnify and hold harmless the repository maintainers from any claims, damages, or liabilities arising from your use of the AMD copyrighted files.
By contributing to this open-source repository, you agree to the RapidStream Contributor License Agreement.
Under this agreement, you grant to RapidStream Design Automation, Inc. and to recipients of software distributed by RapidStream a perpetual, worldwide, non-exclusive, no-charge, royalty-free, irrevocable copyright license to reproduce, prepare derivative works of, publicly display, publicly perform, sublicense, and distribute your contributions and such derivative works. You also grant to RapidStream Design Automation, Inc. and to recipients of software distributed by RapidStream a perpetual, worldwide, non-exclusive, no-charge, royalty-free, irrevocable patent license to make, have made, use, offer to sell, sell, import, and otherwise transfer the work,
Please note that this is a summary of the licensing terms, and the full text of the MIT and the RapidStream Contributor License Agreement should be consulted for detailed legal information.
Copyright (c) 2024 RapidStream Design Automation, Inc. and contributors. All rights reserved.
Below list some common issues user may encounter.
Error Message:
...
File "/home/vagrantxiao24/.rapidstream/opt/python3.10/lib/python3.10/subprocess.py", line 1863, in _execute_child
raise child_exception_type(errno_num, err_msg, err_filename)
FileNotFoundError: [Errno 2] No such file or directory: 'vivado'
make: *** [Makefile:24: rs_opt] Error 1Rapidstream relies on Vivado to compile the designs. If you encounter the error above, you should source the Vivado setup scripts first.
Command to resolve:
source <Vitis_install_path>/Vitis/2023.2/settings64.sh