run_au50.py

"""Getting Started: CNN13x2 in the Vitis flow

This script demonstrates how to optimize a CNN13x2 design in
a Vitis object file. In this example, the object file is generated from the
Vitis_HLS.
"""

__copyright__ = """
Copyright (c) 2024 RapidStream Design Automation, Inc. and contributors.  All rights reserved.
The contributor(s) of this file has/have agreed to the RapidStream Contributor License Agreement.
"""

from rapidstream import get_u50_default_device, RapidStreamHLS, IpiProjectConverter
import os
import shutil
from pathlib import Path
from glob import glob

CURR_DIR = os.path.dirname(os.path.abspath(__file__))

kernel_clk_mhz = 300
hbm_clk_mhz = 300
temp_dir = "build"
kernel_name = "kernel3"
card = "au50"

hdl_src_dir = f"{CURR_DIR}/{temp_dir}/hdl"
ipi_prj_name = (
    f"{CURR_DIR}/{temp_dir}/{kernel_name}_{card}_{kernel_clk_mhz}_{hbm_clk_mhz}M_cl_prj"
)
txt_prj_name = f"{CURR_DIR}/{temp_dir}/{kernel_name}_{card}_{kernel_clk_mhz}_{hbm_clk_mhz}M_cl_txt_prj"
hls_dir = f"{CURR_DIR}/{temp_dir}/{kernel_name}/solution"

verilog_input_dirs: list[str] = [
    hdl_src_dir,
    ipi_prj_name,
]
hls_solution_dirs = [f"{hls_dir}/syn/verilog"]
xdc_input_dirs: list[str] = []

IpiProjectConverter(
    verilog_input_dirs,
    hls_solution_dirs,
    xdc_input_dirs,
).ipi_to_text_prj("cl", txt_prj_name)

shutil.copytree(
    f"{hls_dir}/syn/report",
    f"{txt_prj_name}/hls/solution/syn/report",
    dirs_exist_ok=True,
)

shell_path = f"{temp_dir}/shell_{card}_{kernel_clk_mhz}_{hbm_clk_mhz}M_prj/shell.dcp"

rs = RapidStreamHLS(
    work_dir=Path(f"{temp_dir}/run"),
    hls_flatten_threshold=5,
)

rs.set_virtual_device(get_u50_default_device())
rs.set_shell_path(shell_path)
rs.add_hls_solution(Path(f"{txt_prj_name}/hls/solution"))
rs.add_vlog_files([Path(f) for f in glob(f"{txt_prj_name}/hdl/*.v")])
rs.add_xci_files(
    [Path(f) for f in glob(f"{txt_prj_name}/xci/**/*.xci", recursive=True)]
)
rs.add_iface_only_xci_files(
    [Path(f) for f in glob(f"{txt_prj_name}/iface_only_xci/**/*.xci", recursive=True)]
)

rs.set_top_module_name("cl")
rs.add_flatten_targets([kernel_name])

rs.add_clock("CLK_HBM", 3)
rs.add_clock("CLK_KL", 3)
rs.add_clock("CLK_XDMA", 4)

rs.assign_port_to_region(".*", "SLOT_X0Y0:SLOT_X1Y0")

rs.run_dse(max_workers=2)


## Replace with RapidStreamVitis for the  ".xo" files generated by `v++`.
## Create a RapidStream project in the "run" directory:
# rs = RapidStreamVitis(f"{CURR_DIR}/build")
#
## Use the "xilinx_u50_gen3x16_xdma_5_202210_1" platform as the device:
# u50_factory = get_u50_vitis_device_factory("xilinx_u50_gen3x16_xdma_5_202210_1")
# rs.set_virtual_device(u50_factory.generate_virtual_device())
#
## Add the design object file (".xo") to the project:
# rs.add_xo_file(f"{CURR_DIR}/build/kernel3.xo")
#
## Specify the Vitis platform and connectivity configuration:
# rs.set_vitis_platform("xilinx_u50_gen3x16_xdma_5_202210_1")
# rs.set_vitis_connectivity_config(f"{CURR_DIR}/design/link_config_hbm.ini")
#
## Set the clock target for the design:
# rs.add_clock("ap_clk", period_ns=3)
#
## Bind all ports to HBM 16-31:
# rs.assign_port_to_region(".*", "SLOT_X1Y0:SLOT_X1Y0")
#
## Start the RapidStream optimization process:
# rs.run_dse(skip_impl=True)