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My first successful attempt on building a RISC-V CPU.

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RISC-V 32-bit CPU

Semi-Short Description

A simple CPU that I've written in Verilog for a school project.
This is a pretty bad design, but it's my first one.
I DO NOT recommend using it in the real world.
Issues and Pull Requests are appreciated!

Features

  • ISA: RV32I
  • Multi-Cycle CPU
  • No Pipelining
  • Upto 4 GiB RAM
  • Von-Neumann Architecture
  • Unaligned Memory Access
  • Inspired by: Ben Eaters 8-bit CPU, LMARV-1 (Robert Baruch)
  • No interrupts
  • No Privilleged ISA
  • Phase-Shifted Memory Clock

Supported Memory Attached Devices

Device File
Synchronous Static RAM RAM.v
ROM InstructionROM.v
LEDs & Switches IOController.v
4x 7 Segment Display SevenSegmentController.v
32x GPIO Pins GPIOController.v
SSRAM (without UAM) AlignedRAM.v

Known differences from the specification

  • FENCE and ECALL are NOPs
  • EBREAK halts the processor (hlt=1)

Known bugs

  • reset doesn't work

Tested on

  • ModelSim-Altera
  • DE10-Lite (12.5MHz)

TODO (priority: top=highest)

  • Writing a bootloader
  • Finding bugs and fixing them
  • Documentation and Comments
  • Add DDR2 SDR-SDRAM Controller
  • More Useful README
  • Extending the architecture

How YOU can help me

I couldn't find any useful and cheap rescources for designing hardware in Verilog.
I would appreciate it if you could provide the knowledge that I'm searching for.
Google and DuckDuckGo only found beginner's tutorials for Verilog newbies.
My topics of interest are:

  • Deeper Computer Design
  • SDRAM Controller for DE10-Lite
  • SPI master/slave Languages of choice: English, German

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