Release v5.0.1

renesas · Nov 9, 2023 · 1b4a994 · 1b4a994
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diff --git a/README.md b/README.md
@@ -10,7 +10,7 @@ FSP uses an open software ecosystem and provides flexibility in using your prefe
 
 ### Current Release
 
-[FSP v5.0.0](https://github.com/renesas/fsp/releases/tag/v5.0.0)
+[FSP v5.0.1](https://github.com/renesas/fsp/releases/tag/v5.0.1)
 
 ### Supported RA MCU Kits
 
@@ -85,7 +85,7 @@ When using the zipped version of the packs the zip file should be extracted into
 
 #### For new users that are using FSP with e² studio
 
-1.	Download the FSP with e² studio Installer from the Assets section of the [current release](https://github.com/renesas/fsp/releases/tag/v5.0.0).
+1.	Download the FSP with e² studio Installer from the Assets section of the [current release](https://github.com/renesas/fsp/releases/tag/v5.0.1).
 2.	Run the installer. This will install the e² studio tool, FSP packs, GCC toolchain and other tools required to use this software. No additional installations are required.
 
 #### If using RA Smart Configurator (RASC) with IAR Embedded Workbench or Keil MDK ####

diff --git a/SUPPORTED_SOFTWARE.md b/SUPPORTED_SOFTWARE.md
@@ -361,7 +361,7 @@
     * [Crypto AES2](https://renesas.github.io/fsp/)
     * [Crypto RA2](https://renesas.github.io/fsp/)
     * [FreeRTOS MbedTLS Port](https://renesas.github.io/fsp/)
-    * [Key Injection for PSA Crypto](https://renesas.github.io/fsp/group___s_c_e___k_e_y___i_n_j_e_c_t_i_o_n.html)
+    * [Key Injection for PSA Crypto](https://renesas.github.io/fsp/group___r_s_i_p___k_e_y___i_n_j_e_c_t_i_o_n.html)
     * [MCUBoot TinyCrypt H/W Acceleration (rm_mcuboot_tinycrypt_port)](https://renesas.github.io/fsp/group___r_m___t_i_n_y_c_r_y_p_t___p_o_r_t.html)
     * [MCUboot TinyCrypt (H/W Accelerated)](https://github.com/01org/tinycrypt/blob/master/documentation/tinycrypt.rst)
     * [MCUboot TinyCrypt (S/W Only)](https://github.com/01org/tinycrypt/blob/master/documentation/tinycrypt.rst)

diff --git a/ra/fsp/inc/fsp_version.h b/ra/fsp/inc/fsp_version.h
@@ -48,16 +48,16 @@ extern "C" {
  #define FSP_VERSION_MINOR (0U)
 
 /** FSP pack patch version. */
- #define FSP_VERSION_PATCH (0U)
+ #define FSP_VERSION_PATCH (1U)
 
 /** FSP pack version build number (currently unused). */
  #define FSP_VERSION_BUILD           (0U)
 
 /** Public FSP version name. */
- #define FSP_VERSION_STRING          ("5.0.0")
+ #define FSP_VERSION_STRING          ("5.0.1")
 
 /** Unique FSP version ID. */
- #define FSP_VERSION_BUILD_STRING    ("Built with Renesas Advanced Flexible Software Package version 5.0.0")
+ #define FSP_VERSION_BUILD_STRING    ("Built with Renesas Advanced Flexible Software Package version 5.0.1")
 
 /**********************************************************************************************************************
  * Typedef definitions

diff --git a/ra/fsp/src/bsp/mcu/all/bsp_clocks.c b/ra/fsp/src/bsp/mcu/all/bsp_clocks.c
@@ -954,6 +954,8 @@ void bsp_prv_clock_set (uint32_t clock, uint32_t sckdivcr, uint8_t sckdivcr2)
     if (g_clock_freq[clock] >= g_clock_freq[R_SYSTEM->SCKSCR])
     {
 #if BSP_CFG_CLOCK_SETTLING_DELAY_ENABLE
+        bool post_div_set_delay = false;
+
         if ((clock_freq_hz_post_change > SystemCoreClock) &&
             ((clock_freq_hz_post_change - SystemCoreClock) > BSP_MAX_CLOCK_CHANGE_THRESHOLD))
         {
@@ -995,15 +997,31 @@ void bsp_prv_clock_set (uint32_t clock, uint32_t sckdivcr, uint8_t sckdivcr2)
             /* Wait for settling delay. */
             SystemCoreClockUpdate();
             R_BSP_SoftwareDelay(BSP_CFG_CLOCK_SETTLING_DELAY_US, BSP_DELAY_UNITS_MICROSECONDS);
+
+            /* Trigger delay after setting dividers */
+            post_div_set_delay = true;
         }
         /* Continue and set clock to actual target speed. */
 #endif
 
         /* Set the clock dividers before switching to the new clock source. */
         prv_clock_dividers_set(sckdivcr, sckdivcr2);
 
-        /* Switch to the new clock source. */
-        R_SYSTEM->SCKSCR = (uint8_t) clock;
+#if BSP_CFG_CLOCK_SETTLING_DELAY_ENABLE
+        if (post_div_set_delay)
+        {
+            /* Update the CMSIS core clock variable so that it reflects the new ICLK frequency. */
+            SystemCoreClock = clock_freq_hz_post_change;
+
+            /* Wait for settling delay. */
+            R_BSP_SoftwareDelay(BSP_CFG_CLOCK_SETTLING_DELAY_US, BSP_DELAY_UNITS_MICROSECONDS);
+        }
+        else
+#endif
+        {
+            /* Switch to the new clock source. */
+            R_SYSTEM->SCKSCR = (uint8_t) clock;
+        }
     }
     /* Switching to a slower source clock. */
     else
@@ -1206,6 +1224,10 @@ static void bsp_prv_clock_set_hard_reset (void)
     /* Continue and set clock to actual target speed. */
     R_SYSTEM->SCKDIVCR2 = BSP_PRV_STARTUP_SCKDIVCR2;
     R_SYSTEM->SCKDIVCR  = BSP_PRV_STARTUP_SCKDIVCR;
+
+    /* Wait for settling delay. */
+    SystemCoreClockUpdate();
+    R_BSP_SoftwareDelay(BSP_CFG_CLOCK_SETTLING_DELAY_US, BSP_DELAY_UNITS_MICROSECONDS);
    #else
     #if BSP_PRV_ICLK_DIV_VALUE >= BSP_PRV_SCKDIVCR_DIV_VALUE(BSP_FEATURE_CGC_ICLK_DIV_RESET)
 

diff --git a/ra/fsp/src/bsp/mcu/ra8m1/bsp_feature.h b/ra/fsp/src/bsp/mcu/ra8m1/bsp_feature.h
@@ -30,12 +30,13 @@
  **********************************************************************************************************************/
 
 /** The main oscillator drive value is based upon the oscillator frequency selected in the configuration */
+#define CGC_MOMCR_RESERVED_MASK    (0x8U) /* RA8 has reserved bit in MOMCR that must be 1. */
 #if (BSP_CFG_XTAL_HZ > (24000000))
- #define CGC_MAINCLOCK_DRIVE    (0x05U)
+ #define CGC_MAINCLOCK_DRIVE       (0x05U | CGC_MOMCR_RESERVED_MASK)
 #elif (BSP_CFG_XTAL_HZ > (8000000)) && (BSP_CFG_XTAL_HZ <= (24000000))
- #define CGC_MAINCLOCK_DRIVE    (0x03U)
+ #define CGC_MAINCLOCK_DRIVE       (0x03U | CGC_MOMCR_RESERVED_MASK)
 #else
- #define CGC_MAINCLOCK_DRIVE    (0x00U)
+ #define CGC_MAINCLOCK_DRIVE       (0x00U | CGC_MOMCR_RESERVED_MASK)
 #endif
 
 /***********************************************************************************************************************
@@ -185,7 +186,7 @@
 #define BSP_FEATURE_CGC_LOW_VOLTAGE_MAX_FREQ_HZ              (0U)       // This MCU does not have Low Voltage Mode
 #define BSP_FEATURE_CGC_MIDDLE_SPEED_MAX_FREQ_HZ             (0U)       // This MCU does not have Middle Speed Mode
 #define BSP_FEATURE_CGC_MOCO_STABILIZATION_MAX_US            (15U)
-#define BSP_FEATURE_CGC_MODRV_MASK                           (R_SYSTEM_MOMCR_MODRV0_Msk)
+#define BSP_FEATURE_CGC_MODRV_MASK                           (0x1EU)
 #define BSP_FEATURE_CGC_MODRV_SHIFT                          (R_SYSTEM_MOMCR_MODRV0_Pos)
 #define BSP_FEATURE_CGC_PLL_OUT_MAX_HZ                       (480000000U)
 #define BSP_FEATURE_CGC_PLL_OUT_P_MAX_HZ                     (480000000U)

diff --git a/ra/fsp/src/rm_at_transport_da16xxx_uart/rm_at_transport_da16xxx_uart.c b/ra/fsp/src/rm_at_transport_da16xxx_uart/rm_at_transport_da16xxx_uart.c
@@ -928,25 +928,25 @@ static void rm_at_transport_da16xxx_cleanup_open (at_transport_da16xxx_ctrl_t *
         p_instance_ctrl->uart_tei_sem[AT_TRANSPORT_DA16XXX_UART_INITIAL_PORT] = NULL;
     }
 
+    uart_instance_t * p_uart = p_instance_ctrl->uart_instance_objects[AT_TRANSPORT_DA16XXX_UART_INITIAL_PORT];
+    if (SCIU_OPEN == ((rm_at_transport_da16xxx_uart_instance_ctrl_t *) p_uart->p_ctrl)->open)
+    {
+        p_uart->p_api->close(p_uart->p_ctrl);
+    }
+
     if (p_instance_ctrl->num_uarts > 1)
     {
         if (NULL != p_instance_ctrl->uart_tei_sem[AT_TRANSPORT_DA16XXX_UART_SECOND_PORT])
         {
             vSemaphoreDelete(p_instance_ctrl->uart_tei_sem[AT_TRANSPORT_DA16XXX_UART_SECOND_PORT]);
             p_instance_ctrl->uart_tei_sem[AT_TRANSPORT_DA16XXX_UART_SECOND_PORT] = NULL;
         }
-    }
-
-    uart_instance_t * p_uart = p_instance_ctrl->uart_instance_objects[AT_TRANSPORT_DA16XXX_UART_INITIAL_PORT];
-    if (SCIU_OPEN == ((rm_at_transport_da16xxx_uart_instance_ctrl_t *) p_uart->p_ctrl)->open)
-    {
-        p_uart->p_api->close(p_uart->p_ctrl);
-    }
 
-    p_uart = p_instance_ctrl->uart_instance_objects[AT_TRANSPORT_DA16XXX_UART_SECOND_PORT];
-    if (SCIU_OPEN == ((rm_at_transport_da16xxx_uart_instance_ctrl_t *) p_uart->p_ctrl)->open)
-    {
-        p_uart->p_api->close(p_uart->p_ctrl);
+        p_uart = p_instance_ctrl->uart_instance_objects[AT_TRANSPORT_DA16XXX_UART_SECOND_PORT];
+        if (SCIU_OPEN == ((rm_at_transport_da16xxx_uart_instance_ctrl_t *) p_uart->p_ctrl)->open)
+        {
+            p_uart->p_api->close(p_uart->p_ctrl);
+        }
     }
 }
 

diff --git a/ra/fsp/src/rm_emwin_port/GUI_X_OS.c b/ra/fsp/src/rm_emwin_port/GUI_X_OS.c
@@ -83,19 +83,15 @@ void GUI_X_Delay (int Period)
 #else
     uint32_t time_start = g_gui_time_ms;
 
- #if BSP_CFG_RTOS_SLEEP_MODE_DELAY_ENABLE
-    bool clock_slowed = bsp_prv_clock_prepare_pre_sleep();
- #endif
-
     /* Wait for the specified number of ticks */
     do
     {
+ #if !defined(BSP_CFG_RTOS_IDLE_SLEEP) || BSP_CFG_RTOS_IDLE_SLEEP
         __WFI();
-    } while ((int) (g_gui_time_ms - time_start) < Period);
-
- #if BSP_CFG_RTOS_SLEEP_MODE_DELAY_ENABLE
-    bsp_prv_clock_prepare_post_sleep(clock_slowed);
+ #else
+        R_BSP_SoftwareDelay(1, BSP_DELAY_UNITS_MICROSECONDS);
  #endif
+    } while ((int) (g_gui_time_ms - time_start) < Period);
 #endif
 }
 

diff --git a/ra/fsp/src/rm_freertos_port/port.c b/ra/fsp/src/rm_freertos_port/port.c
@@ -1297,7 +1297,9 @@ void vPortExitCritical (void)
  **********************************************************************************************************************/
 void rm_freertos_port_sleep_preserving_lpm (uint32_t xExpectedIdleTime)
 {
+ #if !defined(BSP_CFG_RTOS_IDLE_SLEEP) || BSP_CFG_RTOS_IDLE_SLEEP
     uint32_t saved_lpm_state = 0U;
+ #endif
 
     /* Sleep until something happens.  configPRE_SLEEP_PROCESSING() can
      * set its parameter to 0 to indicate that its implementation contains
@@ -1307,16 +1309,18 @@ void rm_freertos_port_sleep_preserving_lpm (uint32_t xExpectedIdleTime)
     configPRE_SLEEP_PROCESSING(xExpectedIdleTime);
     if (xExpectedIdleTime > 0)
     {
+ #if !defined(BSP_CFG_RTOS_IDLE_SLEEP) || BSP_CFG_RTOS_IDLE_SLEEP
+
         /* Save LPM Mode */
- #if BSP_FEATURE_LPM_HAS_SBYCR_SSBY
+  #if BSP_FEATURE_LPM_HAS_SBYCR_SSBY
         saved_lpm_state = R_SYSTEM->SBYCR;
- #elif BSP_FEATURE_LPM_HAS_LPSCR
+  #elif BSP_FEATURE_LPM_HAS_LPSCR
         saved_lpm_state = R_SYSTEM->LPSCR;
- #endif
+  #endif
 
         /** Check if the LPM peripheral is set to go to Software Standby mode with WFI instruction.
          *  If so, change the LPM peripheral to go to Sleep mode. */
- #if BSP_FEATURE_LPM_HAS_SBYCR_SSBY
+  #if BSP_FEATURE_LPM_HAS_SBYCR_SSBY
         if (R_SYSTEM_SBYCR_SSBY_Msk & saved_lpm_state)
         {
             /* Save register protect value */
@@ -1332,43 +1336,39 @@ void rm_freertos_port_sleep_preserving_lpm (uint32_t xExpectedIdleTime)
             R_SYSTEM->PRCR = (uint16_t) (RM_FREERTOS_PORT_LOCK_LPM_REGISTER_ACCESS | saved_prcr);
         }
 
- #elif BSP_FEATURE_LPM_HAS_LPSCR
+  #elif BSP_FEATURE_LPM_HAS_LPSCR
         if (R_SYSTEM_LPSCR_LPMD_Msk & saved_lpm_state)
         {
-  #if BSP_TZ_NONSECURE_BUILD
+   #if BSP_TZ_NONSECURE_BUILD
 
             /* Save register protect value */
             uint32_t saved_prcr = R_SYSTEM->PRCR_NS;
 
             /* Unlock LPM peripheral registers */
             R_SYSTEM->PRCR_NS = RM_FREERTOS_PORT_UNLOCK_LPM_REGISTER_ACCESS;
-  #else
+   #else
 
             /* Save register protect value */
             uint32_t saved_prcr = R_SYSTEM->PRCR;
 
             /* Unlock LPM peripheral registers */
             R_SYSTEM->PRCR = RM_FREERTOS_PORT_UNLOCK_LPM_REGISTER_ACCESS;
-  #endif
+   #endif
 
             /* Clear to set to sleep low power mode (not standby or deep standby) */
             R_SYSTEM->LPSCR = 0U;
 
-  #if BSP_TZ_NONSECURE_BUILD
+   #if BSP_TZ_NONSECURE_BUILD
 
             /* Restore register lock */
             R_SYSTEM->PRCR_NS = (uint16_t) (RM_FREERTOS_PORT_LOCK_LPM_REGISTER_ACCESS | saved_prcr);
-  #else
+   #else
 
             /* Restore register lock */
             R_SYSTEM->PRCR = (uint16_t) (RM_FREERTOS_PORT_LOCK_LPM_REGISTER_ACCESS | saved_prcr);
-  #endif
+   #endif
         }
- #endif
-
- #if BSP_CFG_RTOS_SLEEP_MODE_DELAY_ENABLE
-        bool clock_slowed = bsp_prv_clock_prepare_pre_sleep();
- #endif
+  #endif
 
         /**
          * DSB should be last instruction executed before WFI
@@ -1384,10 +1384,14 @@ void rm_freertos_port_sleep_preserving_lpm (uint32_t xExpectedIdleTime)
 
         /* Instruction Synchronization Barrier. */
         __ISB();
+ #else
 
- #if BSP_CFG_RTOS_SLEEP_MODE_DELAY_ENABLE
-        bsp_prv_clock_prepare_post_sleep(clock_slowed);
- #endif
+        /* Wait for an interrupt to be pending without going to sleep if BSP is configured to not sleep when idle for RTOS. */
+        while (0 == (SCB->ICSR & SCB_ICSR_VECTPENDING_Msk))
+        {
+            R_BSP_SoftwareDelay(1, BSP_DELAY_UNITS_MICROSECONDS);;
+        }
+ #endif                                /* !defined(BSP_CFG_RTOS_IDLE_SLEEP) || BSP_CFG_RTOS_IDLE_SLEEP */
 
         /* Re-enable interrupts to allow the interrupt that brought the MCU
          * out of sleep mode to execute immediately. This will not cause a
@@ -1401,9 +1405,11 @@ void rm_freertos_port_sleep_preserving_lpm (uint32_t xExpectedIdleTime)
 
     configPOST_SLEEP_PROCESSING(xExpectedIdleTime);
 
+ #if !defined(BSP_CFG_RTOS_IDLE_SLEEP) || BSP_CFG_RTOS_IDLE_SLEEP
+
     /** Check if the LPM peripheral was supposed to go to Software Standby mode with WFI instruction.
      *  If yes, restore the LPM peripheral setting. */
- #if BSP_FEATURE_LPM_HAS_SBYCR_SSBY
+  #if BSP_FEATURE_LPM_HAS_SBYCR_SSBY
     if (R_SYSTEM_SBYCR_SSBY_Msk & saved_lpm_state)
     {
         /* Save register protect value */
@@ -1419,38 +1425,39 @@ void rm_freertos_port_sleep_preserving_lpm (uint32_t xExpectedIdleTime)
         R_SYSTEM->PRCR = (uint16_t) (RM_FREERTOS_PORT_LOCK_LPM_REGISTER_ACCESS | saved_prcr);
     }
 
- #elif BSP_FEATURE_LPM_HAS_LPSCR
+  #elif BSP_FEATURE_LPM_HAS_LPSCR
     if (R_SYSTEM_LPSCR_LPMD_Msk & saved_lpm_state)
     {
-  #if BSP_TZ_NONSECURE_BUILD
+   #if BSP_TZ_NONSECURE_BUILD
 
         /* Save register protect value */
         uint32_t saved_prcr = R_SYSTEM->PRCR_NS;
 
         /* Unlock LPM peripheral registers */
         R_SYSTEM->PRCR_NS = RM_FREERTOS_PORT_UNLOCK_LPM_REGISTER_ACCESS;
-  #else
+   #else
 
         /* Save register protect value */
         uint32_t saved_prcr = R_SYSTEM->PRCR;
 
         /* Unlock LPM peripheral registers */
         R_SYSTEM->PRCR = RM_FREERTOS_PORT_UNLOCK_LPM_REGISTER_ACCESS;
-  #endif
+   #endif
 
         /* Restore LPM Mode */
         R_SYSTEM->LPSCR = (uint8_t) saved_lpm_state;
 
-  #if BSP_TZ_NONSECURE_BUILD
+   #if BSP_TZ_NONSECURE_BUILD
 
         /* Restore register lock */
         R_SYSTEM->PRCR_NS = (uint16_t) (RM_FREERTOS_PORT_LOCK_LPM_REGISTER_ACCESS | saved_prcr);
-  #else
+   #else
 
         /* Restore register lock */
         R_SYSTEM->PRCR = (uint16_t) (RM_FREERTOS_PORT_LOCK_LPM_REGISTER_ACCESS | saved_prcr);
-  #endif
+   #endif
     }
+  #endif
  #endif
 }