Release v5.4.0

renesas · Jun 27, 2024 · bd5dbaf · bd5dbaf
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diff --git a/LICENSE.md b/LICENSE.md
@@ -12,7 +12,7 @@
 | rm_motor_speed<br>(pre-compiled libraries)            | Renesas Electronics Corporation    | [Renesas Software License Agreement](https://www.renesas.com/us/en/document/oth/disclaimer002)|
 | rm_zmod4xxx<br>(pre-compiled libraries)               | Renesas Electronics Corporation    | [Renesas Software License Agreement](https://www.renesas.com/us/en/document/oth/disclaimer002)|
 |<tr> <td colspan="3"><strong>Third-Party components included in the packs<strong></td></tr>                                                                                               |
-| [CMSIS](https://github.com/ARM-software/CMSIS_5)      | ARM Limited                        | Apache-2.0 License                                                                          |
+| [CMSIS](https://github.com/ARM-software/CMSIS_6)      | ARM Limited                        | Apache-2.0 License                                                                          |
 | [CMSIS Pack](https://github.com/Open-CMSIS-Pack)      | ARM Limited                        | Apache-2.0 License                                                                          |
 | [CMSIS DSP](https://github.com/ARM-software/CMSIS-DSP)| ARM Limited                        | Apache-2.0 License                                                                          |
 | [CMSISNN](https://github.com/ARM-software/CMSIS-NN)   | ARM Limited                        | Apache-2.0 License                                                                          |

diff --git a/README.md b/README.md
@@ -10,7 +10,7 @@ FSP uses an open software ecosystem and provides flexibility in using your prefe
 
 ### Current Release
 
-[FSP v5.3.0](https://github.com/renesas/fsp/releases/tag/v5.3.0)
+[FSP v5.4.0](https://github.com/renesas/fsp/releases/tag/v5.4.0)
 
 ### Supported RA MCU Kits
 
@@ -25,8 +25,10 @@ FSP uses an open software ecosystem and provides flexibility in using your prefe
 - FPB-RA2E3
 - FPB-RA4E1
 - FPB-RA4E2
+- FPB-RA4T1
 - FPB-RA6E1
 - FPB-RA6E2
+- FPB-RA6T3
 - EK-RA2A1
 - EK-RA2A2
 - EK-RA2E1
@@ -101,7 +103,7 @@ When using the zipped version of the packs the zip file should be extracted into
 
 #### For new users that are using FSP with e² studio
 
-1.	Download the FSP with e² studio Installer from the Assets section of the [current release](https://github.com/renesas/fsp/releases/tag/v5.3.0).
+1.	Download the FSP with e² studio Installer from the Assets section of the [current release](https://github.com/renesas/fsp/releases/tag/v5.4.0).
 2.	Run the installer. This will install the e² studio tool, FSP packs, GCC toolchain and other tools required to use this software. No additional installations are required.
 
 #### If using RA Smart Configurator (RASC) with IAR Embedded Workbench or Keil MDK ####

diff --git a/SUPPORTED_SOFTWARE.md b/SUPPORTED_SOFTWARE.md
diff --git a/ra/board/ra8d1_ek/board.h b/ra/board/ra8d1_ek/board.h
@@ -23,9 +23,9 @@
 
 /* BSP Board Specific Includes. */
 #include "board_init.h"
-#include "board_sdram.h"
 #include "board_leds.h"
 #include "board_ethernet_phy.h"
+#include "../../src/bsp/mcu/all/board_sdram.h"
 
 /***********************************************************************************************************************
  * Macro definitions

diff --git a/ra/board/ra8d1_ek/board_sdram.c b/ra/board/ra8d1_ek/board_sdram.c
diff --git a/ra/fsp/inc/api/bsp_api.h b/ra/fsp/inc/api/bsp_api.h
@@ -65,6 +65,10 @@
  #include "../../src/bsp/mcu/all/bsp_delay.h"
  #include "../../src/bsp/mcu/all/bsp_mcu_api.h"
 
+ #if __has_include("../../src/bsp/mcu/all/internal/bsp_internal.h")
+  #include "../../src/bsp/mcu/all/internal/bsp_internal.h"
+ #endif
+
 #endif
 
 /** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */

diff --git a/ra/fsp/inc/api/r_cgc_api.h b/ra/fsp/inc/api/r_cgc_api.h
@@ -88,14 +88,15 @@ typedef enum e_cgc_pll_div
 /** PLL clock output divisor. */
 typedef enum e_cgc_pll_out_div
 {
-    CGC_PLL_OUT_DIV_2  = 2,            ///< PLL output clock divided by 2
-    CGC_PLL_OUT_DIV_3  = 3,            ///< PLL output clock divided by 3
-    CGC_PLL_OUT_DIV_4  = 4,            ///< PLL output clock divided by 4
-    CGC_PLL_OUT_DIV_5  = 5,            ///< PLL output clock divided by 5
-    CGC_PLL_OUT_DIV_6  = 6,            ///< PLL output clock divided by 6
-    CGC_PLL_OUT_DIV_8  = 8,            ///< PLL output clock divided by 8
-    CGC_PLL_OUT_DIV_9  = 9,            ///< PLL output clock divided by 9
-    CGC_PLL_OUT_DIV_16 = 16,           ///< PLL output clock divided by 16
+    CGC_PLL_OUT_DIV_2   = 2,           ///< PLL output clock divided by 2
+    CGC_PLL_OUT_DIV_3   = 3,           ///< PLL output clock divided by 3
+    CGC_PLL_OUT_DIV_4   = 4,           ///< PLL output clock divided by 4
+    CGC_PLL_OUT_DIV_5   = 5,           ///< PLL output clock divided by 5
+    CGC_PLL_OUT_DIV_6   = 6,           ///< PLL output clock divided by 6
+    CGC_PLL_OUT_DIV_8   = 8,           ///< PLL output clock divided by 8
+    CGC_PLL_OUT_DIV_9   = 9,           ///< PLL output clock divided by 9
+    CGC_PLL_OUT_DIV_1_5 = 10,          ///< PLL output clock divided by 1.5
+    CGC_PLL_OUT_DIV_16  = 16,          ///< PLL output clock divided by 16
 } cgc_pll_out_div_t;
 
 #ifndef BSP_OVERRIDE_CGC_SYS_CLOCK_DIV_T

diff --git a/ra/fsp/inc/api/r_crc_api.h b/ra/fsp/inc/api/r_crc_api.h
@@ -72,9 +72,9 @@ typedef enum e_crc_snoop_direction
 /** Structure for CRC inputs */
 typedef struct st_crc_input_t
 {
-    uint32_t num_bytes;                // Length of input buffer
-    uint32_t crc_seed;                 // CRC seed value
-    void   * p_input_buffer;           // Pointer to input buffer
+    uint32_t     num_bytes;            ///< Length of input buffer. It must be 4-byte aligned when a 32-bit CRC polynomial function is used.
+    uint32_t     crc_seed;             ///< CRC seed value
+    const void * p_input_buffer;       ///< Pointer to input buffer
 } crc_input_t;
 
 /** CRC control block.  Allocate an instance specific control block to pass into the CRC API calls.

diff --git a/ra/fsp/inc/api/r_ether_api.h b/ra/fsp/inc/api/r_ether_api.h
@@ -96,7 +96,13 @@ typedef enum e_ether_event
     ETHER_EVENT_WAKEON_LAN,            ///< Magic packet detection event
     ETHER_EVENT_LINK_ON,               ///< Link up detection event
     ETHER_EVENT_LINK_OFF,              ///< Link down detection event
-    ETHER_EVENT_INTERRUPT,             ///< Interrupt event
+    ETHER_EVENT_INTERRUPT,             ///< DEPRECATED Interrupt event
+    ETHER_EVENT_RX_COMPLETE,           ///< Receive complete event.
+    ETHER_EVENT_RX_MESSAGE_LOST,       ///< Receive FIFO overflow or Receive descriptor is full.
+    ETHER_EVENT_TX_COMPLETE,           ///< Transmit complete event.
+    ETHER_EVENT_TX_BUFFER_EMPTY,       ///< Transmit descriptor or FIFO is empty.
+    ETHER_EVENT_TX_ABORTED,            ///< Transmit abort event.
+    ETHER_EVENT_ERR_GLOBAL,            ///< Global error has occurred.
 } ether_event_t;
 #endif
 

diff --git a/ra/fsp/inc/api/r_i2c_master_api.h b/ra/fsp/inc/api/r_i2c_master_api.h
@@ -60,7 +60,9 @@ typedef enum e_i2c_master_event
 {
     I2C_MASTER_EVENT_ABORTED     = 1,  ///< A transfer was aborted
     I2C_MASTER_EVENT_RX_COMPLETE = 2,  ///< A receive operation was completed successfully
-    I2C_MASTER_EVENT_TX_COMPLETE = 3   ///< A transmit operation was completed successfully
+    I2C_MASTER_EVENT_TX_COMPLETE = 3,  ///< A transmit operation was completed successfully
+    I2C_MASTER_EVENT_START       = 4,  ///< I2C sent a start condition
+    I2C_MASTER_EVENT_BYTE_ACK    = 5,  ///< I2C finished sending/receiving 1 data byte
 } i2c_master_event_t;
 
 /** I2C callback parameter definition */