High Performance Processors and Systems Project

Bluespec RISC-V processors

Abstract: Bluespec System Verilog (BSV) is a state-of-the-art Hardware Description Language (HDL).
Bluespec compilation toolchain (BSC) has been recently released as open source.
The purpose of this project is to investigate the potentiality of its toolchain implementing a multi-stage RISC-V processor.

Keyword: Bluespec, RISC-V, Computer Architectures

Final report of the project here

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Requirements to run the examples:

• bsc

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How to run the examples:

Compile into Verilog RTL

$ bsc -verilog filename.bsv

where filename.bsv is your BSV file

Simulate your design from Verilog RTL

$ bsc -o sim -e moduleName moduleName.v
$ ./sim

where sim is the desired output executable name, moduleName is the top-level module in the design and moduleName.v is the output of the previous step.

Test your design with a testbench

In order to use Bluespec's native simulator Bluesim to simulate the design and generate the VCD we compile the sources to Bluesim objects:

$ bsc -u -sim testbench.bsv

where testbench.bsv is your source testbench file, and create the executable with:

$ bsc -o sim -sim -e moduleName

where sim is the desired output executable name and moduleName is the top-level module in the testbench source.

We can then execute the executable and dump the waveforms in a .vcd file

$ ./sim -V dump.vcd

where sim is the output of the previous step and dump.vcd is the desired .vcd output file.

This 3 steps are automated in a really simple bash script testbench.sh, more info on the use of the script are avaiable through

$ ./testbench.sh -h