dsync

rizinorg · Nov 18, 2024 · d5db582 · d5db582
1 parent dc5bc2b
commit d5db582
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diff --git a/librz/arch/isa/xtensa/xtensa_il.c b/librz/arch/isa/xtensa/xtensa_il.c
@@ -433,6 +433,7 @@ static RzAnalysisLiftedILOp op_div0_s(XtensaContext *ctx) {
 	return SETG(REGN(0), UNSIGNED(64, F2BV(FDIV(RZ_FLOAT_RMODE_RNA, FLOATV32(IREG(0)), FLOATV32(IREG(1))))));
 }
 
+// FIXME: statusflags
 static RzAnalysisLiftedILOp op_divn_s(XtensaContext *ctx) {
 	return SEQ4(
 		SETL("fr", FLOATV32(IREG(0))),
@@ -441,6 +442,10 @@ static RzAnalysisLiftedILOp op_divn_s(XtensaContext *ctx) {
 		SETG(REGN(0), UNSIGNED(64, F2BV(FADD(RZ_FLOAT_RMODE_RNA, VARL("fr"), FMUL(RZ_FLOAT_RMODE_RNA, VARL("fs"), FNEG(VARL("ft"))))))));
 }
 
+static RzAnalysisLiftedILOp op_dsync(XtensaContext *ctx) {
+	return NOP();
+}
+
 #include <rz_il/rz_il_opbuilder_end.h>
 
 static const fn_analyze_op_il fn_tbl[] = {
@@ -505,6 +510,7 @@ static const fn_analyze_op_il fn_tbl[] = {
 	[XTENSA_INS_CONST_S] = op_const_s,
 	[XTENSA_INS_DIV0_S] = op_div0_s,
 	[XTENSA_INS_DIVN_S] = op_divn_s,
+	[XTENSA_INS_DSYNC] = op_dsync,
 };
 
 void xtensa_analyze_op_rzil(XtensaContext *ctx, RzAnalysisOp *op) {

diff --git a/test/db/asm/xtensa b/test/db/asm/xtensa
@@ -69,3 +69,4 @@ d "clamps a2, a3, 8" 102333 0x0 (seq (set low (float 0 (bv 32 0x43800000) )) (se
 d "const.s f4, 3" 3043fa 0x0 (set f4 (cast 64 false (fbits (float 0 (bv 32 0x3f000000) ))))
 d "div0.s f1, f2" 7012fa 0x0 (set f1 (cast 64 false (fbits (/. rna (float 0 (var f1) ) (float 0 (var f2) )))))
 d "divn.s f2, f3, f1" 10237a 0x0 (seq (set fr (float 0 (var f2) )) (set fs (float 0 (var f3) )) (set ft (float 0 (var f1) )) (set f2 (cast 64 false (fbits (+. rna (var fr) (*. rna (var fs) (fneg (var ft))))))))
+d "dsync" 302000 0x0 nop