SCCL is an open-source tool that translates synthesizable SystemC to SystemVerilog RTL. This project started out as front-end for parsing and analyzing SystemC models, and it has evolved into a translator with the addition of a HDL synthesis plugin.
- llvm/clang (version 15.0.6)
- SystemC version 2.3.3.
- c++14 is required. We are using some features that necessitate c++17. Down-porting it is also possible, but not supported.
- Please see this
To compile with the HDL plugin, run cmake with the -DHDL=on flag.
Doxygen: https://anikau31.github.io/systemc-clang/index.html
It is possible to build the documentation by specifying the
-DBUILD_DOC=ONflag. This will provide the following targetsdoxygen: Builds Doxygen documentation.sphinx: Builds Sphinx documentation.
To enable compilation of tests, run cmake with the -DENABLE_TESTS=on flag and also the -DSYSTEMC_DIR=<path> flag to pass the location for SystemC. Without specifying the SYSTEMC_DIR path, it will not be possible to run the unit tests.
For information about running verilog conversion tests, see this file.
If you encounter problems, please create issues with a minimally working example that illustrates the issue.
We build all the dependencies necessary for SCCL in a Docker image that you may use. Follow these Docker SCCL instructions to use the Docker image for building SCCL, and running benchmarks.
If you're interested in contributing to SCCL, then we keep a list of interesting projects that one could approach. Please consult projects.
- Zhuanhao Wu, Maya Gokhale, Scott Lloyd and Hiren Patel, SCCL: An open-source SystemC to RTL translator, 2023 IEEE 31st Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), Marina Del Rey, CA, USA, 2023, pp. 23-33, doi: 10.1109/FCCM57271.2023.00012.
- Zhuanhao Wu
- Maya B. Gokhale
|SCCL| follows the same licensing as clang. Please look at LICENSE.