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Merge pull request #24 from tsemo4917/add-hypervisor-timer-ctl-reg
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add CNTHP_CTL_EL2 register
nchong-at-aws authored Feb 20, 2024

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2 parents a4af226 + 04b32e5 commit 040d0ec
Showing 2 changed files with 65 additions and 0 deletions.
2 changes: 2 additions & 0 deletions src/registers.rs
Original file line number Diff line number Diff line change
@@ -22,6 +22,7 @@ mod ccsidr_el1;
mod clidr_el1;
mod cntfrq_el0;
mod cnthctl_el2;
mod cnthp_ctl_el2;
mod cntkctl_el1;
mod cntp_ctl_el0;
mod cntp_cval_el0;
@@ -109,6 +110,7 @@ pub use ccsidr_el1::CCSIDR_EL1;
pub use clidr_el1::CLIDR_EL1;
pub use cntfrq_el0::CNTFRQ_EL0;
pub use cnthctl_el2::CNTHCTL_EL2;
pub use cnthp_ctl_el2::CNTHP_CTL_EL2;
pub use cntkctl_el1::CNTKCTL_EL1;
pub use cntp_ctl_el0::CNTP_CTL_EL0;
pub use cntp_cval_el0::CNTP_CVAL_EL0;
63 changes: 63 additions & 0 deletions src/registers/cnthp_ctl_el2.rs
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@@ -0,0 +1,63 @@
// SPDX-License-Identifier: Apache-2.0 OR MIT
//
// Copyright (c) 2018-2023 by the author(s)
//
// Author(s):
// - tsemo4917 <tsemo4917@users.noreply.github.com>

//! Counter-timer Hypervisor Physical Timer Control Register - EL2
//!
//! Control register for the EL2 physical timer.
use tock_registers::{
interfaces::{Readable, Writeable},
register_bitfields,
};

register_bitfields! {u64,
pub CNTHP_CTL_EL2 [
/// The status of the timer. This bit indicates whether the timer condition is met:
///
/// 0 Timer condition is not met.
/// 1 Timer condition is met.
///
/// When the value of the ENABLE bit is 1, ISTATUS indicates whether the timer condition is
/// met. ISTATUS takes no account of the value of the IMASK bit. If the value of ISTATUS is
/// 1 and the value of IMASK is 0 then the timer interrupt is asserted.
///
/// When the value of the ENABLE bit is 0, the ISTATUS field is UNKNOWN.
///
/// This bit is read-only.
ISTATUS OFFSET(2) NUMBITS(1) [],

/// Timer interrupt mask bit. Permitted values are:
///
/// 0 Timer interrupt is not masked by the IMASK bit.
/// 1 Timer interrupt is masked by the IMASK bit.
IMASK OFFSET(1) NUMBITS(1) [],

/// Enables the timer. Permitted values are:
///
/// 0 Timer disabled.
/// 1 Timer enabled.
ENABLE OFFSET(0) NUMBITS(1) []
]
}

pub struct Reg;

impl Readable for Reg {
type T = u64;
type R = CNTHP_CTL_EL2::Register;

sys_coproc_read_raw!(u64, "CNTHP_CTL_EL2", "x");
}

impl Writeable for Reg {
type T = u64;
type R = CNTHP_CTL_EL2::Register;

sys_coproc_write_raw!(u64, "CNTHP_CTL_EL2", "x");
}

pub const CNTHP_CTL_EL2: Reg = Reg {};

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