Merge branch 'master' into riscv-pac

riscv-rt/CHANGELOG.md

@@ -22,6 +22,8 @@ If `v-trap` feature is enabled, this macro also generates its corresponding trap
 - Made `cfg` variable selection more robust for custom targets
 - `_start_trap_rust` now only deals with exceptions. When an interrupt is detected, it now calls
 to `_dispatch_core_interrupt`.
+- Upgrade rust-version to 1.61
+- Update `syn` to version 2.0
 
 ### Removed
 

riscv-rt/Cargo.toml

@@ -1,7 +1,7 @@
 [package]
 name = "riscv-rt"
 version = "0.13.0"
-rust-version = "1.60"
+rust-version = "1.61"
 repository = "https://github.com/rust-embedded/riscv"
 authors = ["The RISC-V Team <risc-v@teams.rust-embedded.org>"]
 categories = ["embedded", "no-std"]

riscv-rt/README.md

@@ -11,7 +11,7 @@ This project is developed and maintained by the [RISC-V team][team].
 
 ## Minimum Supported Rust Version (MSRV)
 
-This crate is guaranteed to compile on stable Rust 1.60 and up. It *might*
+This crate is guaranteed to compile on stable Rust 1.61 and up. It *might*
 compile with older versions but that may change in any new patch release.
 
 ## License

riscv-rt/macros/Cargo.toml

@@ -19,10 +19,7 @@ proc-macro = true
 [dependencies]
 quote = "1.0"
 proc-macro2 = "1.0"
-
-[dependencies.syn]
-version = "1.0"
-features = ["extra-traits", "full"]
+syn = { version = "2.0", features = ["extra-traits", "full"] }
 
 [features]
 s-mode = []

riscv-rt/src/lib.rs

@@ -2,7 +2,7 @@
 //!
 //! # Minimum Supported Rust Version (MSRV)
 //!
-//! This crate is guaranteed to compile on stable Rust 1.60 and up. It *might*
+//! This crate is guaranteed to compile on stable Rust 1.61 and up. It *might*
 //! compile with older versions but that may change in any new patch release.
 //!
 //! # Features

riscv/CHANGELOG.md

@@ -21,6 +21,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 - Export `riscv::register::macros` module macros for external use
 - Add `riscv::register::mcountinhibit` module for `mcountinhibit` CSR
 - Add `Mcounteren` in-memory update functions 
+- Add `Mstatus` vector extension support
 
 ### Changed
 

riscv/src/register/mstatus.rs

@@ -41,6 +41,15 @@ pub enum FS {
     Dirty = 3,
 }
 
+/// Vector extension state
+#[derive(Copy, Clone, Debug, Eq, PartialEq)]
+pub enum VS {
+    Off = 0,
+    Initial = 1,
+    Clean = 2,
+    Dirty = 3,
+}
+
 /// Machine Previous Privilege Mode
 #[derive(Copy, Clone, Debug, Eq, PartialEq)]
 pub enum MPP {
@@ -216,6 +225,19 @@ impl Mstatus {
         }
     }
 
+    /// Vector extension state
+    #[inline]
+    pub fn vs(&self) -> VS {
+        let fs = bf_extract(self.bits, 9, 2); // bits 9-10
+        match fs {
+            0b00 => VS::Off,
+            0b01 => VS::Initial,
+            0b10 => VS::Clean,
+            0b11 => VS::Dirty,
+            _ => unreachable!(),
+        }
+    }
+
     /// Update Floating-point extension state
     ///
     /// Note this updates a previously read [`Mstatus`] value, but does not
@@ -226,6 +248,16 @@ impl Mstatus {
         self.bits = bf_insert(self.bits, 13, 2, fs as usize);
     }
 
+    /// Update vector extension state
+    ///
+    /// Note this updates a previously read [`Mstatus`] value, but does not
+    /// affect the mstatus CSR itself. See [`set_vs`] to directly update the
+    /// CSR.
+    #[inline]
+    pub fn set_vs(&mut self, vs: VS) {
+        self.bits = bf_insert(self.bits, 9, 2, vs as usize);
+    }
+
     /// Additional extension state
     ///
     /// Encodes the status of additional user-mode extensions and associated
@@ -559,6 +591,15 @@ pub unsafe fn set_fs(fs: FS) {
     _write(value);
 }
 
+/// Vector extension state
+#[inline]
+pub unsafe fn set_vs(vs: VS) {
+    let mut value = _read();
+    value &= !(0x3 << 9); // clear previous value
+    value |= (vs as usize) << 9;
+    _write(value);
+}
+
 /// Set S-mode non-instruction-fetch memory endianness
 ///
 /// # Note