Fix clippy

riscv-peripheral/src/plic.rs

@@ -148,7 +148,7 @@ pub(crate) mod test {
 
     #[pac_enum(unsafe InterruptNumber)]
     #[derive(Clone, Copy, Debug, Eq, PartialEq)]
-    #[repr(u16)]
+    #[repr(usize)]
     pub(crate) enum Interrupt {
         I1 = 1,
         I2 = 2,

riscv-peripheral/src/plic/enables.rs

@@ -30,7 +30,7 @@ impl ENABLES {
     /// Checks if an interrupt source is enabled for the PLIC context.
     #[inline]
     pub fn is_enabled<I: ExternalInterruptNumber>(self, source: I) -> bool {
-        let source = source.number() as usize;
+        let source = source.number();
         let offset = (source / u32::BITS as usize) as _;
         // SAFETY: valid interrupt number
         let reg: Reg<u32, RW> = unsafe { Reg::new(self.ptr.offset(offset)) };
@@ -48,7 +48,7 @@ impl ENABLES {
     /// * Enabling an interrupt source can break mask-based critical sections.
     #[inline]
     pub unsafe fn enable<I: ExternalInterruptNumber>(self, source: I) {
-        let source = source.number() as usize;
+        let source = source.number();
         let offset = (source / u32::BITS as usize) as _;
         // SAFETY: valid interrupt number
         let reg: Reg<u32, RW> = unsafe { Reg::new(self.ptr.offset(offset)) };
@@ -73,7 +73,7 @@ impl ENABLES {
         source: I,
         order: core::sync::atomic::Ordering,
     ) {
-        let source = source.number() as usize;
+        let source = source.number();
         let offset = (source / u32::BITS as usize) as _;
         // SAFETY: valid interrupt number
         let reg: Reg<u32, RW> = unsafe { Reg::new(self.ptr.offset(offset)) };
@@ -87,7 +87,7 @@ impl ENABLES {
     /// It performs non-atomic read-modify-write operations, which may lead to **wrong** behavior.
     #[inline]
     pub fn disable<I: ExternalInterruptNumber>(self, source: I) {
-        let source = source.number() as usize;
+        let source = source.number();
         let offset = (source / u32::BITS as usize) as _;
         // SAFETY: valid interrupt number
         let reg: Reg<u32, RW> = unsafe { Reg::new(self.ptr.offset(offset)) };
@@ -111,7 +111,7 @@ impl ENABLES {
         source: I,
         order: core::sync::atomic::Ordering,
     ) {
-        let source = source.number() as usize;
+        let source = source.number();
         let offset = (source / u32::BITS as usize) as _;
         // SAFETY: valid interrupt number
         let reg: Reg<u32, RW> = unsafe { Reg::new(self.ptr.offset(offset)) };

riscv-peripheral/src/plic/pendings.rs

@@ -30,7 +30,7 @@ impl PENDINGS {
     /// Checks if an interrupt triggered by a given source is pending.
     #[inline]
     pub fn is_pending<I: ExternalInterruptNumber>(self, source: I) -> bool {
-        let source = source.number() as usize;
+        let source = source.number();
         let offset = (source / u32::BITS as usize) as _;
         // SAFETY: valid interrupt number
         let reg: Reg<u32, RO> = unsafe { Reg::new(self.ptr.offset(offset)) };

riscv-peripheral/src/plic/priorities.rs

@@ -31,7 +31,7 @@ impl PRIORITIES {
     #[inline]
     pub fn get_priority<I: ExternalInterruptNumber, P: PriorityNumber>(self, source: I) -> P {
         // SAFETY: valid interrupt number
-        let reg: Reg<u32, RW> = unsafe { Reg::new(self.ptr.offset(source.number() as _)) };
+        let reg: Reg<u32, RW> = unsafe { Reg::new(self.ptr.add(source.number())) };
         P::from_number(reg.read() as _).unwrap()
     }
 
@@ -47,7 +47,7 @@ impl PRIORITIES {
         priority: P,
     ) {
         // SAFETY: valid interrupt number
-        let reg: Reg<u32, RW> = unsafe { Reg::new(self.ptr.offset(source.number() as _)) };
+        let reg: Reg<u32, RW> = unsafe { Reg::new(self.ptr.add(source.number())) };
         reg.write(priority.number() as _);
     }