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The MTIP bit in mip register is read-only #62
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This should be a mistake, we should check and delete them in future releases. |
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108: fix: clearify that mip.{MSIP, MTIP} are read-only r=almindor a=luojia65 closes #62 In RISC-V privileged specification, it says: > Bits mip.MTIP and mie.MTIE are the interrupt-pending and interrupt-enable bits for machine timer interrupts. MTIP is read-only in mip, and is cleared by writing to the memory-mapped machine-mode timer compare register. > > Bits mip.MSIP and mie.MSIE are the interrupt-pending and interrupt-enable bits for machine-level software interrupts. MSIP is read-only in mip, and is written by accesses to memory-mapped control registers, which are used by remote harts to provide machine-level interprocessor interrupts. indicated by the specification, mip.MSIP and mip.MTIP bits are read-only. This pull request clearifies this by removing {set, clear}_{msoft, mtimer} functions from mip module of riscv crate. Co-authored-by: luojia65 <me@luojia.cc>
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62: Preserve .eh_frame and .eh_frame_hdr r=almindor a=Disasm Preserving the `.eh_frame` section improves gdb stack traces on nightly. Preserving the `.eh_frame_hdr` section fixes the linker problem `rust-lld: error: no memory region specified for section '.eh_frame_hdr'` introduced in rust-lang/rust#73564 Co-authored-by: Vadim Kaushan <admin@disasm.info>
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In the
riscv-privileged
manual, it is said that "The MTIP bit (in mip) is read-only and is cleared by writing to the memory-mapped machine-mode timer compare register."But in the
riscv
crate, there is an interface like this:We can write the code
mip::set_mtimer()
to set the 7th bit, the MTIP bit, of the mip register, which does not permitted inriscv-privileged
manual.Is there some reason for the existence of
mip::set_mtimer()
? If not, I suggest remove it.Thanks.
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