add Thumbs to the compiler #36874

japaric · 2016-09-30T21:16:14Z

this commit adds 4 new target definitions to the compiler for easier
cross compilation to ARM Cortex-M devices.

thumbv6m-none-eabi
- For the Cortex-M0, Cortex-M0+ and Cortex-M1
- This architecture doesn't have hardware support (instructions) for
  atomics. Hence, the Atomic* structs are not available for this
  target.
thumbv7m-none-eabi
- For the Cortex-M3
thumbv7em-none-eabi
- For the FPU-less variants of the Cortex-M4 and Cortex-M7
- On this target, all the floating point operations will be lowered
  software routines (intrinsics)
thumbv7em-none-eabihf
- For the variants of the Cortex-M4 and Cortex-M7 that do have a FPU.
- On this target, all the floating point operations will be lowered
  to hardware instructions

No binary releases of standard crates, like core, are planned for
these targets because Cargo, in the future, will compile e.g. the core
crate on the fly as part of the cargo build process. In the meantime,
you'll have to compile the core crate yourself. Xargo is the easiest
way to do that as in handles the compilation of core automatically and
can be used just like Cargo: xargo build --target thumbv6m-none-eabi
is all that's needed.

cc @brson @alexcrichton

rust-highfive · 2016-09-30T21:16:21Z

Thanks for the pull request, and welcome! The Rust team is excited to review your changes, and you should hear from @arielb1 (or someone else) soon.

If any changes to this PR are deemed necessary, please add them as extra commits. This ensures that the reviewer can see what has changed since they last reviewed the code. Due to the way GitHub handles out-of-date commits, this should also make it reasonably obvious what issues have or haven't been addressed. Large or tricky changes may require several passes of review and changes.

Please see the contribution instructions for more information.

alexcrichton · 2016-09-30T23:16:53Z

👍
👎

japaric

Oh, I meant to left this comment earlier but didn't realize I clicked the start review thing. 🤦

japaric · 2016-09-30T21:18:52Z

src/librustc_back/target/mod.rs

@@ -698,6 +707,10 @@ impl ToJson for Target {
        target_option_val!(max_atomic_width);
        target_option_val!(panic_strategy);

+        if self.options.max_atomic_width.to_string() != self.target_pointer_width {


@alexcrichton this fixes the problem I was seeing where setting max_atomic_width to 0 in the Target declaration was being converted into 32 due to the JSON roundtrip. I've also added a rmake test for this.

Woah can't we use Option instead of magic 0 treatment or similar? Granted, I'm arriving late to this issue so apologies if that has already been ruled out for good reason.

This was the simplest change necessary to make this work but using Option here sounds better; I'll give it a try.

bors · 2016-10-01T06:49:28Z

☔ The latest upstream changes (presumably #36339) made this pull request unmergeable. Please resolve the merge conflicts.

this commit adds 4 new target definitions to the compiler for easier cross compilation to ARM Cortex-M devices. - `thumbv6m-none-eabi` - For the Cortex-M0, Cortex-M0+ and Cortex-M1 - This architecture doesn't have hardware support (instructions) for atomics. Hence, the `Atomic*` structs are not available for this target. - `thumbv7m-none-eabi` - For the Cortex-M3 - `thumbv7em-none-eabi` - For the FPU-less variants of the Cortex-M4 and Cortex-M7 - On this target, all the floating point operations will be lowered software routines (intrinsics) - `thumbv7em-none-eabihf` - For the variants of the Cortex-M4 and Cortex-M7 that do have a FPU. - On this target, all the floating point operations will be lowered to hardware instructions No binary releases of standard crates, like `core`, are planned for these targets because Cargo, in the future, will compile e.g. the `core` crate on the fly as part of the `cargo build` process. In the meantime, you'll have to compile the `core` crate yourself. [Xargo] is the easiest way to do that as in handles the compilation of `core` automatically and can be used just like Cargo: `xargo build --target thumbv6m-none-eabi` is all that's needed. [Xargo]: https://crates.io/crates/xargo

japaric · 2016-10-02T21:00:46Z

Pushed two new commits. The first changes relocation-model to static (from pic) and the second changes panic-strategy to abort (from unwind). These values differ from the RFC text but I asked about these changes in the associated PR and the response has been positive so far.

parched · 2016-10-02T21:45:24Z

src/librustc_back/target/thumbv7em_none_eabihf.rs

+
+        options: TargetOptions {
+            // vfp4 lowest common denominator between the Cortex-M4 (vfp4) and the Cortex-M7 (vfp5)
+            features: "+vfp4".to_string(),


I believe you also need +fp-only-sp

Hmm, won't that preclude a user from enabling double precision hardware acceleration? Perhaps they'll have to pass -fp-only-sp apart from the other feature that enables DP FP ops. (I'm speculating; I haven't tried any of this)

Yes -fp-only-sp would work to switch it back on. +d16 should probably be added here too.

Done! Thank you @parched.

alexcrichton · 2016-10-03T18:05:35Z

@japaric could you also add some comments to each target file in line with the RFC itself? Basically just some basic rationale for the target name, what it's intended to be used for, etc.

to better express the idea that omitting this field defaults this value to target_pointer_width

alexcrichton · 2016-10-04T15:16:46Z

@bors: r+

Thanks @japaric!

bors · 2016-10-04T15:16:47Z

📌 Commit 6136069 has been approved by alexcrichton

bors · 2016-10-04T15:29:41Z

⌛ Testing commit 6136069 with merge a5dac7a...

@brson

add Thumbs to the compiler this commit adds 4 new target definitions to the compiler for easier cross compilation to ARM Cortex-M devices. - `thumbv6m-none-eabi` - For the Cortex-M0, Cortex-M0+ and Cortex-M1 - This architecture doesn't have hardware support (instructions) for atomics. Hence, the `Atomic*` structs are not available for this target. - `thumbv7m-none-eabi` - For the Cortex-M3 - `thumbv7em-none-eabi` - For the FPU-less variants of the Cortex-M4 and Cortex-M7 - On this target, all the floating point operations will be lowered software routines (intrinsics) - `thumbv7em-none-eabihf` - For the variants of the Cortex-M4 and Cortex-M7 that do have a FPU. - On this target, all the floating point operations will be lowered to hardware instructions No binary releases of standard crates, like `core`, are planned for these targets because Cargo, in the future, will compile e.g. the `core` crate on the fly as part of the `cargo build` process. In the meantime, you'll have to compile the `core` crate yourself. [Xargo] is the easiest way to do that as in handles the compilation of `core` automatically and can be used just like Cargo: `xargo build --target thumbv6m-none-eabi` is all that's needed. [Xargo]: https://crates.io/crates/xargo --- cc @brson @alexcrichton

bors · 2016-10-04T18:53:05Z

rust-highfive assigned arielb1 Sep 30, 2016

japaric mentioned this pull request Sep 30, 2016

[DoNotMerge][WIP] add support for thumb* (Cortex-M) targets #36526

Closed

3 tasks

japaric commented Sep 30, 2016

View reviewed changes

japaric force-pushed the thumbs branch from 5eb44ca to d44bdc5 Compare October 1, 2016 13:20

japaric mentioned this pull request Oct 2, 2016

Add Cortex-M targets to the compiler + binary releases of core rust-lang/rfcs#1645

Closed

Jorge Aparicio added 4 commits October 2, 2016 15:52

rustc -> $(RUSTC) in rmake test

e4c3263

set relocation-model to static

396b757

set panic-strategy to abort

6d0b8ae

japaric force-pushed the thumbs branch from d44bdc5 to 6d0b8ae Compare October 2, 2016 20:57

parched suggested changes Oct 2, 2016

View reviewed changes

alexcrichton assigned alexcrichton and unassigned arielb1 Oct 3, 2016

Jorge Aparicio added 4 commits October 3, 2016 22:28

add +d16 and +fp-only-sp to thumbv7em-none-eabihf and documentation

cbc56f1

add a reference about the stated FP facts

470eff7

fix: "abort" -> PanicStrategy

251f04e

change max_atomic_width type from u64 to Option<u64>

6136069

to better express the idea that omitting this field defaults this value to target_pointer_width

bors merged commit 6136069 into rust-lang:master Oct 4, 2016

japaric deleted the thumbs branch October 4, 2016 18:53

japaric mentioned this pull request Oct 5, 2016

Cargo doesn't work out of the box for Cortex-M micros rust-embedded/wg#9

Closed

SimonSapin mentioned this pull request Oct 9, 2016

Undefined reference to `__swbuf_r' (and many others) on nightly 2016-10-07 jamesmunns/teensy3-rs#13

Closed

fabricedesre mentioned this pull request Oct 27, 2016

Add support for 'arm-none-eabi' rust-lang/rustup#464

Closed

davidtwco mentioned this pull request Sep 20, 2023

target tier policy compliance #116004

Closed

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add Thumbs to the compiler #36874

add Thumbs to the compiler #36874

japaric commented Sep 30, 2016

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add Thumbs to the compiler #36874

add Thumbs to the compiler #36874

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