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bump mipsel isa leval and enable fpxx #48874

Merged
merged 3 commits into from
Mar 14, 2018
Merged

bump mipsel isa leval and enable fpxx #48874

merged 3 commits into from
Mar 14, 2018

Commits on Mar 8, 2018

  1. librustc_back: bump ISA level of mipsel targets to mips32r2

    @jcowgill
    jcowgill committed Mar 8, 2018
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  2. librustc_back: enable fpxx on 32-bit hardfloat mips targets 

    See this page for details about FPXX:
https://dmz-portal.mips.com/wiki/MIPS_O32_ABI_-_FR0_and_FR1_Interlinking

Using FPXX is the most compatible floating point mode available and
allows the generated code to work in both FR0 and FR1 modes of the
processor. Using MSA (MIPS SIMD) requires FR1, so to use any MSA code we
need a compatible floating point mode.

This commit also sets nooddspreg (disabling the use of odd numbered
single precision float registers) as recommended when enabling FPXX.
    @jcowgill
    jcowgill committed Mar 8, 2018
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  3. librustc_trans: add fp64 to mips features whitelist 

    On 32-bit MIPS, enabling MSA requires also enabling the 64-bit FPU.
    @jcowgill
    jcowgill committed Mar 8, 2018
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