va_args implementation for AAPCS.

[JamieCunliffe]

Implement the va args in codegen for AAPCS, this will be used as the
default va_args implementation for AArch64 rather than the va_args
llvm-ir as it currently is.

This should fix the following issues:
#56475
#72579

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[petrochenkov]

r? @nikic (I guess)

[JamieCunliffe]

@bjorn3 I addressed your comment but force pushed, sorry about that

@dlrobertson - Bringing this to your attention seeing so you commented on the issue regarding this

[dlrobertson]

@JamieCunliffe Thanks for this! I'm not super familiar with the AAPCS64 spec, but on a cursory glance it looks great.

[nikic]

For reference, this is the clang implementation of aapcs va_arg handling: https://github.com/llvm/llvm-project/blob/9548697df9c6f65a3dba4e8de4d015650e73101c/clang/lib/CodeGen/TargetInfo.cpp#L5795

I had a bunch of questions here, but then I realized that Rust's va_arg intrinsic only supports integer and float types, so we don't need handling for any of the "interesting" cases, like homogeneous aggregates.

My remaining question here would be why we can assume a little endian target.

[nikic]

As a mild preference, I would align to the given alignment here, even if 16 is currently the only possibility.

[JamieCunliffe]

I think the assert was unnecessary and I was being a little over cautious, according to the AAPCS 16 is the given alignment for this (https://github.com/ARM-software/abi-aa/blob/master/aapcs64/aapcs64.rst#the-va-arg-macro).

if (alignof(type) > 8)
    offs = (offs + 15) & -16;   // round up

It should only be done on the general purpose registers though and I had missed that in the above check so I have fixed that.

[dlrobertson]

Tested locally and things look good!

I had a bunch of questions here, but then I realized that Rust's va_arg intrinsic only supports integer and float types, so we don't need handling for any of the "interesting" cases, like homogeneous aggregates.

Yeah IIRC we wouldn't be able to rely on the va_arg instruction as much (even for x86_64) if we were to support the interesting cases.

[JamieCunliffe]

My remaining question here would be why we can assume a little endian target.

Lack of actual hardware for testing this, I didn't have any hardware available internally to be able to run this so we decided it was best to have the assert.

[nikic]

My remaining question here would be why we can assume a little endian target.

Lack of actual hardware for testing this, I didn't have any hardware available internally to be able to run this so we decided it was best to have the assert.

Okay, sounds reasonable.

@bors r+ rollup=always

[bors]

📌 Commit 8b58eb9 has been approved by nikic