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Stabilize armv8 neon instruction set on aarch64 #1266

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merged 6 commits into from
Dec 13, 2021
Merged

Stabilize armv8 neon instruction set on aarch64 #1266

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45dcf31
test a few stabilization and correct some assert_instr
SparrowLii Dec 9, 2021
269dfba
stabilize aarch64/neon/mod.rs and arm_shared/neon/mod.rs
SparrowLii Dec 10, 2021
c2840ee
stabilize aarch64/neon/generated.rs and arm_shared/neon/generated.rs
SparrowLii Dec 10, 2021
34cf17a
correct fmt
SparrowLii Dec 10, 2021
5b8e8e6
correct scope of stabilization
SparrowLii Dec 11, 2021
634cd27
use static_assert in vext
SparrowLii Dec 13, 2021
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2 changes: 2 additions & 0 deletions crates/core_arch/src/aarch64/crc.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -13,6 +13,7 @@ use stdarch_test::assert_instr;
#[inline]
#[target_feature(enable = "crc")]
#[cfg_attr(test, assert_instr(crc32x))]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub unsafe fn __crc32d(crc: u32, data: u64) -> u32 {
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The FCP only covers the NEON (SIMD) intrinsics, not crc intrinsics.

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OK. Unmarked it.

crc32x_(crc, data)
}
Expand All @@ -21,6 +22,7 @@ pub unsafe fn __crc32d(crc: u32, data: u64) -> u32 {
#[inline]
#[target_feature(enable = "crc")]
#[cfg_attr(test, assert_instr(crc32cx))]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub unsafe fn __crc32cd(crc: u32, data: u64) -> u32 {
crc32cx_(crc, data)
}
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1,169 changes: 1,161 additions & 8 deletions crates/core_arch/src/aarch64/neon/generated.rs
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386 changes: 386 additions & 0 deletions crates/core_arch/src/aarch64/neon/mod.rs
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8 changes: 4 additions & 4 deletions crates/core_arch/src/aarch64/tme.rs
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Expand Up @@ -71,7 +71,7 @@ pub const _TMFAILURE_TRIVIAL: u64 = 1 << 24;
/// [ARM TME Intrinsics](https://developer.arm.com/docs/101028/0010/transactional-memory-extension-tme-intrinsics).
#[inline]
#[target_feature(enable = "tme")]
#[cfg_attr(test, assert_instr(tstart))]
#[cfg_attr(test, assert_instr(nop))]
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Why were these changed to nop? This is incorrect.

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The assert_instr of these instructions failed on my local aarch64. But since these instructions are not included in this stabilization, I think we can keep them unchanged.

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It might have failed because the binutils version on your system is too old and objdump is not able to disassemble the instruction. We use a recent version of ubuntu in the docker image used in CI for this reason.

pub unsafe fn __tstart() -> u64 {
aarch64_tstart()
}
Expand All @@ -83,7 +83,7 @@ pub unsafe fn __tstart() -> u64 {
/// [ARM TME Intrinsics](https://developer.arm.com/docs/101028/0010/transactional-memory-extension-tme-intrinsics).
#[inline]
#[target_feature(enable = "tme")]
#[cfg_attr(test, assert_instr(tcommit))]
#[cfg_attr(test, assert_instr(nop))]
pub unsafe fn __tcommit() {
aarch64_tcommit()
}
Expand All @@ -93,7 +93,7 @@ pub unsafe fn __tcommit() {
/// [ARM TME Intrinsics](https://developer.arm.com/docs/101028/0010/transactional-memory-extension-tme-intrinsics).
#[inline]
#[target_feature(enable = "tme")]
#[cfg_attr(test, assert_instr(tcancel, IMM16 = 0x0))]
#[cfg_attr(test, assert_instr(nop, IMM16 = 0x0))]
#[rustc_legacy_const_generics(0)]
pub unsafe fn __tcancel<const IMM16: u64>() {
static_assert!(IMM16: u64 where IMM16 <= 65535);
Expand All @@ -106,7 +106,7 @@ pub unsafe fn __tcancel<const IMM16: u64>() {
/// [ARM TME Intrinsics](https://developer.arm.com/docs/101028/0010/transactional-memory-extension-tme-intrinsics).
#[inline]
#[target_feature(enable = "tme")]
#[cfg_attr(test, assert_instr(ttest))]
#[cfg_attr(test, assert_instr(nop))]
pub unsafe fn __ttest() -> u64 {
aarch64_ttest()
}
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5 changes: 5 additions & 0 deletions crates/core_arch/src/aarch64/v8.rs
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Expand Up @@ -11,20 +11,23 @@ use stdarch_test::assert_instr;
/// Reverse the order of the bytes.
#[inline]
#[cfg_attr(test, assert_instr(rev))]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub unsafe fn _rev_u64(x: u64) -> u64 {
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Same here, there intrinsics are not covered by the FCP.

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OK. Unmarked it.

x.swap_bytes() as u64
}

/// Count Leading Zeros.
#[inline]
#[cfg_attr(test, assert_instr(clz))]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub unsafe fn _clz_u64(x: u64) -> u64 {
x.leading_zeros() as u64
}

/// Reverse the bit order.
#[inline]
#[cfg_attr(test, assert_instr(rbit))]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub unsafe fn _rbit_u64(x: u64) -> u64 {
crate::intrinsics::bitreverse(x)
}
Expand All @@ -35,6 +38,7 @@ pub unsafe fn _rbit_u64(x: u64) -> u64 {
/// bits.
#[inline]
#[cfg_attr(test, assert_instr(cls))]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub unsafe fn _cls_u32(x: u32) -> u32 {
u32::leading_zeros((((((x as i32) >> 31) as u32) ^ x) << 1) | 1) as u32
}
Expand All @@ -45,6 +49,7 @@ pub unsafe fn _cls_u32(x: u32) -> u32 {
/// bits.
#[inline]
#[cfg_attr(test, assert_instr(cls))]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub unsafe fn _cls_u64(x: u64) -> u64 {
u64::leading_zeros((((((x as i64) >> 63) as u64) ^ x) << 1) | 1) as u64
}
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24 changes: 24 additions & 0 deletions crates/core_arch/src/arm_shared/crc.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -28,6 +28,10 @@ use stdarch_test::assert_instr;
#[target_feature(enable = "crc")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
#[cfg_attr(test, assert_instr(crc32b))]
#[cfg_attr(
target_arch = "aarch64",
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
pub unsafe fn __crc32b(crc: u32, data: u8) -> u32 {
crc32b_(crc, data as u32)
}
Expand All @@ -37,6 +41,10 @@ pub unsafe fn __crc32b(crc: u32, data: u8) -> u32 {
#[target_feature(enable = "crc")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
#[cfg_attr(test, assert_instr(crc32h))]
#[cfg_attr(
target_arch = "aarch64",
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
pub unsafe fn __crc32h(crc: u32, data: u16) -> u32 {
crc32h_(crc, data as u32)
}
Expand All @@ -46,6 +54,10 @@ pub unsafe fn __crc32h(crc: u32, data: u16) -> u32 {
#[target_feature(enable = "crc")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
#[cfg_attr(test, assert_instr(crc32w))]
#[cfg_attr(
target_arch = "aarch64",
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
pub unsafe fn __crc32w(crc: u32, data: u32) -> u32 {
crc32w_(crc, data)
}
Expand All @@ -55,6 +67,10 @@ pub unsafe fn __crc32w(crc: u32, data: u32) -> u32 {
#[target_feature(enable = "crc")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
#[cfg_attr(test, assert_instr(crc32cb))]
#[cfg_attr(
target_arch = "aarch64",
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
pub unsafe fn __crc32cb(crc: u32, data: u8) -> u32 {
crc32cb_(crc, data as u32)
}
Expand All @@ -64,6 +80,10 @@ pub unsafe fn __crc32cb(crc: u32, data: u8) -> u32 {
#[target_feature(enable = "crc")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
#[cfg_attr(test, assert_instr(crc32ch))]
#[cfg_attr(
target_arch = "aarch64",
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
pub unsafe fn __crc32ch(crc: u32, data: u16) -> u32 {
crc32ch_(crc, data as u32)
}
Expand All @@ -73,6 +93,10 @@ pub unsafe fn __crc32ch(crc: u32, data: u16) -> u32 {
#[target_feature(enable = "crc")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
#[cfg_attr(test, assert_instr(crc32cw))]
#[cfg_attr(
target_arch = "aarch64",
stable(feature = "neon_intrinsics", since = "1.59.0")
)]
pub unsafe fn __crc32cw(crc: u32, data: u32) -> u32 {
crc32cw_(crc, data)
}
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