Design and synthesis a circuit to multiply two elements of Galois Field (Secure Hardware Design Assignment)
Design a circuit to multiply two elements of using VHDL language and synthesis the design using AMS C35B4 0.35um technology process as well as perform behavioral and post-synthesis simulation to verify the correct functunality of the design.
In order to design a circuit to multiply two elements of , and by assuming that the circuit has two three bits inputs (InputA, InputB) and one three bits output (Output). The following equation can be concluded:
Therefore, the circuit could be designed to be consisted of combinational logic only, by using Xor gate for each addition and And gate for each multiplication for the last equation obtained. The following figure shows the block diagram of the design.
The following table shows all the possible combinations of the input values and the corresponding output values, based on the fact that the elements of are the remainders of polynomials division over
, Therefore they consist of all polynomials of degree less than 3:
.
By writing a test bench that covers the whole 64 possible cases and running the simulation, the design can be verified by checking that all the output values are the same as the corresponding ones listed in the table.
By writing a test bench that covers the whole 64 possible cases, including the HDL library files for AMS 0.35 um technology and running the simulation, the design can be verified by checking that all the output values are the same as the corresponding ones listed in the table.