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1. verilog-module-generator-for-state-machine verilog-module-generator-for-state-machine Public

   A Python-based tool for generating Verilog modules with features including customizable state machines, port definitions, and state diagrams using Graphviz. Ideal for FPGA and ASIC design workflows.

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2. Dadda-8-bit Dadda-8-bit Public

   The computational speed of the dadda multiplier can be enhanced by partitioning the partial products. In process to achieve low power we have considered pass transistor for logical implementation.

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3. Architectural-Design-for-Bus-interface-connected-with-LFSR Architectural-Design-for-Bus-interface-connected-with-LFSR Public

   bus interface, integrating LFSR’s for streamlined register management. Enabled seamless master-peripheral communication, enhancing system efficiency. Orchestrated comprehensive design stages, yield…

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