- 👋 Hi, I’m @sidhantp1906
- 👀 I’m interested in VLSI Systom on chip design
- 🌱 I’m currently a student with enthusiasm in digital VLSI
- 💞️ I’m looking to collaborate with VLSI teams/companies
- 📫 reach me ..through linkedin -sidhant priyadarshi
-
KLE Technological University
- bihar
- linkedin.com/in/sidhant-priyadarshi-028612185/
Popular repositories Loading
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4-Request-First-Come-First-Serve-Arbiter
4-Request-First-Come-First-Serve-Arbiter Public4 request first come first serve arbiter design using verilog HDL
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RTC-Real-Time-Clock-
RTC-Real-Time-Clock- PublicDesign of real time clock(RTC) using Verilog HDL
Verilog 3
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binary-to-csd
binary-to-csd Publicverilog code to covert binary number into canonical signed digit(csd)
Verilog 2
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Adcanced_Digital_Logic_Design-01fe19bec187
Adcanced_Digital_Logic_Design-01fe19bec187 PublicLab projects using Verilog HDL
Verilog 2
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csd-multiplier-using-booth-technique
csd-multiplier-using-booth-technique Publiccsd multiplier using booth technique in which i have converted binary multiplier into csd and multiplicand is binary.
Verilog 1
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