Merge pull request #490 from sifive/dev_emmanuelp

Fix issue with TRNG when we use simulation
sifive · May 13, 2020 · 4853a1e · 4853a1e
2 parents 227ebb6 + b02f9d2
commit 4853a1e
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Showing 4 changed files with 9 additions and 5 deletions.
diff --git a/scl-metal b/scl-metal
diff --git a/scripts/standalone.mk b/scripts/standalone.mk
@@ -216,10 +216,14 @@ endif
 RISCV_XCFLAGS += -DITERATIONS=$(TARGET_CORE_ITERS)
 endif
 
-ifeq ($(filter freertos,$(PROGRAM)),)
+ifeq ($(findstring freertos,$(PROGRAM)),freertos)
 RISCV_XCFLAGS += -DWAIT_MS=$(TARGET_FREERTOS_WAIT_MS)
 endif
 
+ifneq ($(filter rtl,$(TARGET_TAGS)),)
+RISCV_XCFLAGS += -DHCA_BYPASS_TRNG
+endif
+
 #############################################################
 # Software
 #############################################################

diff --git a/software/example-hca-metal b/software/example-hca-metal
diff --git a/wit-manifest.json b/wit-manifest.json
@@ -250,12 +250,12 @@
         "source": "git@github.com:sifive/example-hpm.git"
     },
     {
-        "commit": "bd09832897db486abff69e8158cb9fd40d6c7a68",
+        "commit": "d0ce5f9c13a28585e2aeb4aed8af9a72a08e3e4d",
         "name": "scl-metal",
         "source": "git@github.com:sifive/scl-metal.git"
     },
     {
-        "commit": "e902018d6aff78a64dc795f9633a7b1e8a2d120b",
+        "commit": "504092a3ed9fbb625ed7f1d6ddb51acabc7da60c",
         "name": "example-hca-metal",
         "source": "git@github.com:sifive/example-hca-metal.git"
     }