Updated QEMU bsp's with larger memories matching QEMU 4.1.0

bsp/qemu-sifive-e31/README.md

@@ -1,4 +1,5 @@
-SiFive QEMU E31 is a virtual development platform matching the Freedom E310. It’s the best way to start prototyping and developing your RISC‑V applications.
+SiFive QEMU E31 is a virtual development platform matching the Freedom E310 (with more memory though).
+It’s the best way to start prototyping and developing your RISC‑V applications.
 
 This target is ideal for getting familiarize with RISC-V ISA instructions set and freedom-metal libraries. It supports:
 
@@ -10,5 +11,6 @@ This target is ideal for getting familiarize with RISC-V ISA instructions set an
 - SPI memory with 1 interrupt line
 - Serial port with 1 interrupt line
 - 1 RGB LEDS
+- DTIM memory with 4M bytes
 
-This BSP matches the QEMU code in https://github.com/sifive/riscv-qemu/tree/riscv-qemu-3.1
+This BSP matches the QEMU code in https://git.qemu.org/?p=qemu.git;a=tree;h=refs/tags/v4.1.0;hb=refs/tags/v4.1.0

bsp/qemu-sifive-e31/design.dts

@@ -87,6 +87,12 @@
                         reg-names = "config";
                 };
 
+                test: test@100000 {
+                        compatible = "sifive,test0";
+                        reg = <0x100000 0x1000>;
+                        reg-names = "control";
+                };
+
                 aon: aon@10000000 {
                         compatible = "sifive,aon0";
                         reg = <0x10000000 0x8000>;
@@ -144,7 +150,7 @@
 
                 dtim: dtim@80000000 {
                         compatible = "sifive,dtim0";
-                        reg = <0x80000000 0x4000>;
+                        reg = <0x80000000 0x400000>;
                         reg-names = "mem";
                 };
 

bsp/qemu-sifive-e31/metal-inline.h

@@ -91,6 +91,8 @@ extern __inline__ unsigned long __metal_driver_sifive_spi0_pinmux_source_selecto
 
 
 /* --------------------- sifive_test0 ------------ */
+extern __inline__ unsigned long __metal_driver_sifive_test0_base(const struct __metal_shutdown *sd);
+extern __inline__ unsigned long __metal_driver_sifive_test0_size(const struct __metal_shutdown *sd);
 
 
 /* --------------------- sifive_uart0 ------------ */
@@ -169,7 +171,7 @@ struct __metal_driver_fixed_clock __metal_dt_clock_5 = {
 
 struct metal_memory __metal_dt_mem_dtim_80000000 = {
     ._base_address = 2147483648UL,
-    ._size = 16384UL,
+    ._size = 4194304UL,
     ._attrs = {
         .R = 1,
         .W = 1,
@@ -248,6 +250,11 @@ struct __metal_driver_sifive_spi0 __metal_dt_spi_10014000 = {
     .spi.vtable = &__metal_driver_vtable_sifive_spi0.spi,
 };
 
+/* From test@100000 */
+struct __metal_driver_sifive_test0 __metal_dt_test_100000 = {
+    .shutdown.vtable = &__metal_driver_vtable_sifive_test0.shutdown,
+};
+
 /* From serial@10013000 */
 struct __metal_driver_sifive_uart0 __metal_dt_serial_10013000 = {
     .uart.vtable = &__metal_driver_vtable_sifive_uart0.uart,

bsp/qemu-sifive-e31/metal-platform.h

@@ -221,6 +221,15 @@
 #define METAL_SIFIVE_SPI0_IE 112UL
 #define METAL_SIFIVE_SPI0_IP 116UL
 
+/* From test@100000 */
+#define METAL_SIFIVE_TEST0_100000_BASE_ADDRESS 1048576UL
+#define METAL_SIFIVE_TEST0_0_BASE_ADDRESS 1048576UL
+#define METAL_SIFIVE_TEST0_100000_SIZE 4096UL
+#define METAL_SIFIVE_TEST0_0_SIZE 4096UL
+
+#define METAL_SIFIVE_TEST0
+#define METAL_SIFIVE_TEST0_FINISHER_OFFSET 0UL
+
 /* From serial@10013000 */
 #define METAL_SIFIVE_UART0_10013000_BASE_ADDRESS 268513280UL
 #define METAL_SIFIVE_UART0_0_BASE_ADDRESS 268513280UL

bsp/qemu-sifive-e31/metal.default.lds

@@ -5,7 +5,7 @@ ENTRY(_enter)
 MEMORY
 {
 	flash (rxai!w) : ORIGIN = 0x20400000, LENGTH = 0x1fc00000
-	ram (wxa!ri) : ORIGIN = 0x80000000, LENGTH = 0x4000
+	ram (wxa!ri) : ORIGIN = 0x80000000, LENGTH = 0x400000
 }
 
 PHDRS

bsp/qemu-sifive-e31/metal.h

@@ -81,6 +81,7 @@
 #include <metal/drivers/sifive_gpio-leds.h>
 #include <metal/drivers/sifive_rtc0.h>
 #include <metal/drivers/sifive_spi0.h>
+#include <metal/drivers/sifive_test0.h>
 #include <metal/drivers/sifive_uart0.h>
 #include <metal/drivers/sifive_wdog0.h>
 #include <metal/drivers/sifive_fe310-g000_hfrosc.h>
@@ -134,6 +135,9 @@ struct __metal_driver_sifive_rtc0 __metal_dt_rtc_10000000;
 /* From spi@10014000 */
 struct __metal_driver_sifive_spi0 __metal_dt_spi_10014000;
 
+/* From test@100000 */
+struct __metal_driver_sifive_test0 __metal_dt_test_100000;
+
 /* From serial@10013000 */
 struct __metal_driver_sifive_uart0 __metal_dt_serial_10013000;
 
@@ -698,6 +702,26 @@ static __inline__ unsigned long __metal_driver_sifive_spi0_pinmux_source_selecto
 
 
 /* --------------------- sifive_test0 ------------ */
+static __inline__ unsigned long __metal_driver_sifive_test0_base(const struct __metal_shutdown *sd)
+{
+	if ((uintptr_t)sd == (uintptr_t)&__metal_dt_test_100000) {
+		return METAL_SIFIVE_TEST0_100000_BASE_ADDRESS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static __inline__ unsigned long __metal_driver_sifive_test0_size(const struct __metal_shutdown *sd)
+{
+	if ((uintptr_t)sd == (uintptr_t)&__metal_dt_test_100000) {
+		return METAL_SIFIVE_TEST0_100000_SIZE;
+	}
+	else {
+		return 0;
+	}
+}
+
 
 
 /* --------------------- sifive_uart0 ------------ */
@@ -1062,6 +1086,11 @@ __asm__ (".weak __metal_spi_table");
 struct __metal_driver_sifive_spi0 *__metal_spi_table[] = {
 					&__metal_dt_spi_10014000};
 
+/* From test@100000 */
+#define __METAL_DT_SHUTDOWN_HANDLE (&__metal_dt_test_100000.shutdown)
+
+#define __METAL_DT_TEST_100000_HANDLE (&__metal_dt_test_100000.shutdown)
+
 #define __METAL_DT_MAX_WDOGS 1
 
 __asm__ (".weak __metal_wdog_table");

bsp/qemu-sifive-e31/metal.ramrodata.lds

@@ -5,7 +5,7 @@ ENTRY(_enter)
 MEMORY
 {
 	flash (rxai!w) : ORIGIN = 0x20400000, LENGTH = 0x1fc00000
-	ram (wxa!ri) : ORIGIN = 0x80000000, LENGTH = 0x4000
+	ram (wxa!ri) : ORIGIN = 0x80000000, LENGTH = 0x400000
 }
 
 PHDRS
@@ -38,15 +38,6 @@ SECTIONS
 		KEEP (*(SORT_NONE(.fini)))
 	} >flash AT>flash :flash
 
-
-
-	.text : {
-		*(.text.unlikely .text.unlikely.*)
-		*(.text.startup .text.startup.*)
-		*(.text .text.*)
-		*(.gnu.linkonce.t.*)
-	} >flash AT>flash :flash
-
 	PROVIDE (__etext = .);
 	PROVIDE (_etext = .);
 	PROVIDE (etext = .);
@@ -92,6 +83,10 @@ SECTIONS
 
 
 	.itim : ALIGN(8) {
+		*(.text.unlikely .text.unlikely.*)
+		*(.text.startup .text.startup.*)
+		*(.text .text.*)
+		*(.gnu.linkonce.t.*)
 		*(.itim .itim.*)
 	} >ram AT>flash :itim_init
 

bsp/qemu-sifive-e31/metal.scratchpad.lds

@@ -4,7 +4,7 @@ ENTRY(_enter)
 
 MEMORY
 {
-	ram (wxa!ri) : ORIGIN = 0x80000000, LENGTH = 0x4000
+	ram (wxa!ri) : ORIGIN = 0x80000000, LENGTH = 0x400000
 }
 
 PHDRS

bsp/qemu-sifive-s51/README.md

@@ -1,4 +1,5 @@
-SiFive QEMU S51 is a virtual development platform matching the Freedom S510. It’s the best way to start prototyping and developing your RISC‑V applications.
+SiFive QEMU S51 is a virtual development platform matching the Freedom S510 (with more memory though).
+It’s the best way to start prototyping and developing your RISC‑V applications.
 
 This target is ideal for getting familiarize with RISC-V ISA instructions set and freedom-metal libraries. It supports:
 
@@ -10,5 +11,6 @@ This target is ideal for getting familiarize with RISC-V ISA instructions set an
 - SPI memory with 1 interrupt line
 - Serial port with 1 interrupt line
 - 1 RGB LEDS
+- DTIM memory with 4M bytes
 
-This BSP matches the QEMU code in https://github.com/sifive/riscv-qemu/tree/riscv-qemu-3.1
+This BSP matches the QEMU code in https://git.qemu.org/?p=qemu.git;a=tree;h=refs/tags/v4.1.0;hb=refs/tags/v4.1.0

bsp/qemu-sifive-s51/design.dts

@@ -87,6 +87,12 @@
                         reg-names = "config";
                 };
 
+                test: test@100000 {
+                        compatible = "sifive,test0";
+                        reg = <0x100000 0x1000>;
+                        reg-names = "control";
+                };
+
                 aon: aon@10000000 {
                         compatible = "sifive,aon0";
                         reg = <0x10000000 0x8000>;
@@ -144,7 +150,7 @@
 
                 dtim: dtim@80000000 {
                         compatible = "sifive,dtim0";
-                        reg = <0x80000000 0x4000>;
+                        reg = <0x80000000 0x400000>;
                         reg-names = "mem";
                 };
 

bsp/qemu-sifive-s51/metal-inline.h

@@ -91,6 +91,8 @@ extern __inline__ unsigned long __metal_driver_sifive_spi0_pinmux_source_selecto
 
 
 /* --------------------- sifive_test0 ------------ */
+extern __inline__ unsigned long __metal_driver_sifive_test0_base(const struct __metal_shutdown *sd);
+extern __inline__ unsigned long __metal_driver_sifive_test0_size(const struct __metal_shutdown *sd);
 
 
 /* --------------------- sifive_uart0 ------------ */
@@ -169,7 +171,7 @@ struct __metal_driver_fixed_clock __metal_dt_clock_5 = {
 
 struct metal_memory __metal_dt_mem_dtim_80000000 = {
     ._base_address = 2147483648UL,
-    ._size = 16384UL,
+    ._size = 4194304UL,
     ._attrs = {
         .R = 1,
         .W = 1,
@@ -248,6 +250,11 @@ struct __metal_driver_sifive_spi0 __metal_dt_spi_10014000 = {
     .spi.vtable = &__metal_driver_vtable_sifive_spi0.spi,
 };
 
+/* From test@100000 */
+struct __metal_driver_sifive_test0 __metal_dt_test_100000 = {
+    .shutdown.vtable = &__metal_driver_vtable_sifive_test0.shutdown,
+};
+
 /* From serial@10013000 */
 struct __metal_driver_sifive_uart0 __metal_dt_serial_10013000 = {
     .uart.vtable = &__metal_driver_vtable_sifive_uart0.uart,

bsp/qemu-sifive-s51/metal-platform.h

@@ -221,6 +221,15 @@
 #define METAL_SIFIVE_SPI0_IE 112UL
 #define METAL_SIFIVE_SPI0_IP 116UL
 
+/* From test@100000 */
+#define METAL_SIFIVE_TEST0_100000_BASE_ADDRESS 1048576UL
+#define METAL_SIFIVE_TEST0_0_BASE_ADDRESS 1048576UL
+#define METAL_SIFIVE_TEST0_100000_SIZE 4096UL
+#define METAL_SIFIVE_TEST0_0_SIZE 4096UL
+
+#define METAL_SIFIVE_TEST0
+#define METAL_SIFIVE_TEST0_FINISHER_OFFSET 0UL
+
 /* From serial@10013000 */
 #define METAL_SIFIVE_UART0_10013000_BASE_ADDRESS 268513280UL
 #define METAL_SIFIVE_UART0_0_BASE_ADDRESS 268513280UL

bsp/qemu-sifive-s51/metal.default.lds

@@ -5,7 +5,7 @@ ENTRY(_enter)
 MEMORY
 {
 	flash (rxai!w) : ORIGIN = 0x20400000, LENGTH = 0x1fc00000
-	ram (wxa!ri) : ORIGIN = 0x80000000, LENGTH = 0x4000
+	ram (wxa!ri) : ORIGIN = 0x80000000, LENGTH = 0x400000
 }
 
 PHDRS

bsp/qemu-sifive-s51/metal.h

@@ -81,6 +81,7 @@
 #include <metal/drivers/sifive_gpio-leds.h>
 #include <metal/drivers/sifive_rtc0.h>
 #include <metal/drivers/sifive_spi0.h>
+#include <metal/drivers/sifive_test0.h>
 #include <metal/drivers/sifive_uart0.h>
 #include <metal/drivers/sifive_wdog0.h>
 #include <metal/drivers/sifive_fe310-g000_hfrosc.h>
@@ -134,6 +135,9 @@ struct __metal_driver_sifive_rtc0 __metal_dt_rtc_10000000;
 /* From spi@10014000 */
 struct __metal_driver_sifive_spi0 __metal_dt_spi_10014000;
 
+/* From test@100000 */
+struct __metal_driver_sifive_test0 __metal_dt_test_100000;
+
 /* From serial@10013000 */
 struct __metal_driver_sifive_uart0 __metal_dt_serial_10013000;
 
@@ -698,6 +702,26 @@ static __inline__ unsigned long __metal_driver_sifive_spi0_pinmux_source_selecto
 
 
 /* --------------------- sifive_test0 ------------ */
+static __inline__ unsigned long __metal_driver_sifive_test0_base(const struct __metal_shutdown *sd)
+{
+	if ((uintptr_t)sd == (uintptr_t)&__metal_dt_test_100000) {
+		return METAL_SIFIVE_TEST0_100000_BASE_ADDRESS;
+	}
+	else {
+		return 0;
+	}
+}
+
+static __inline__ unsigned long __metal_driver_sifive_test0_size(const struct __metal_shutdown *sd)
+{
+	if ((uintptr_t)sd == (uintptr_t)&__metal_dt_test_100000) {
+		return METAL_SIFIVE_TEST0_100000_SIZE;
+	}
+	else {
+		return 0;
+	}
+}
+
 
 
 /* --------------------- sifive_uart0 ------------ */
@@ -1062,6 +1086,11 @@ __asm__ (".weak __metal_spi_table");
 struct __metal_driver_sifive_spi0 *__metal_spi_table[] = {
 					&__metal_dt_spi_10014000};
 
+/* From test@100000 */
+#define __METAL_DT_SHUTDOWN_HANDLE (&__metal_dt_test_100000.shutdown)
+
+#define __METAL_DT_TEST_100000_HANDLE (&__metal_dt_test_100000.shutdown)
+
 #define __METAL_DT_MAX_WDOGS 1
 
 __asm__ (".weak __metal_wdog_table");

bsp/qemu-sifive-s51/metal.ramrodata.lds

@@ -5,7 +5,7 @@ ENTRY(_enter)
 MEMORY
 {
 	flash (rxai!w) : ORIGIN = 0x20400000, LENGTH = 0x1fc00000
-	ram (wxa!ri) : ORIGIN = 0x80000000, LENGTH = 0x4000
+	ram (wxa!ri) : ORIGIN = 0x80000000, LENGTH = 0x400000
 }
 
 PHDRS
@@ -38,15 +38,6 @@ SECTIONS
 		KEEP (*(SORT_NONE(.fini)))
 	} >flash AT>flash :flash
 
-
-
-	.text : {
-		*(.text.unlikely .text.unlikely.*)
-		*(.text.startup .text.startup.*)
-		*(.text .text.*)
-		*(.gnu.linkonce.t.*)
-	} >flash AT>flash :flash
-
 	PROVIDE (__etext = .);
 	PROVIDE (_etext = .);
 	PROVIDE (etext = .);
@@ -92,6 +83,10 @@ SECTIONS
 
 
 	.itim : ALIGN(8) {
+		*(.text.unlikely .text.unlikely.*)
+		*(.text.startup .text.startup.*)
+		*(.text .text.*)
+		*(.gnu.linkonce.t.*)
 		*(.itim .itim.*)
 	} >ram AT>flash :itim_init
 

bsp/qemu-sifive-s51/metal.scratchpad.lds

@@ -4,7 +4,7 @@ ENTRY(_enter)
 
 MEMORY
 {
-	ram (wxa!ri) : ORIGIN = 0x80000000, LENGTH = 0x4000
+	ram (wxa!ri) : ORIGIN = 0x80000000, LENGTH = 0x400000
 }
 
 PHDRS

bsp/qemu-sifive-u54/README.md

@@ -7,4 +7,4 @@ Metal libraries. It supports:
 - 1 hart with support for the RV64GC instruction set
 - A Memory Management Unit with SV48 Virtual Memory
 
-This BSP matches the QEMU code in https://github.com/sifive/riscv-qemu/tree/riscv-qemu-3.1
+This BSP matches the QEMU code in https://git.qemu.org/?p=qemu.git;a=tree;h=refs/tags/v4.1.0;hb=refs/tags/v4.1.0