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Merge pull request #414 from gechiang/202205
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[Chassis][Voq][Yang] Make asic_name case sensitive in yang models (#1
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gechiang authored Jul 13, 2024
2 parents 784ec43 + 28a272b commit 91e01c7
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Showing 5 changed files with 85 additions and 9 deletions.
Original file line number Diff line number Diff line change
Expand Up @@ -86,6 +86,82 @@
]
}
}
},
"SYSTEM_ASIC_NAME_UPPERCASE": {
"sonic-system-port:sonic-system-port": {
"sonic-system-port:SYSTEM_PORT": {
"SYSTEM_PORT_LIST": [
{
"hostname": "host456",
"asic_name": "ASIC0",
"ifname": "Ethernet0",
"core_index": "1",
"core_port_index": "20",
"num_voq": "8",
"speed": "900000",
"switch_id": "1",
"system_port_id": "200"
}
]
}
}
},
"SYSTEM_ASIC_NAME_INVALID": {
"sonic-system-port:sonic-system-port": {
"sonic-system-port:SYSTEM_PORT": {
"SYSTEM_PORT_LIST": [
{
"hostname": "host456",
"asic_name": "INVALIDASIC0",
"ifname": "Ethernet0",
"core_index": "1",
"core_port_index": "20",
"num_voq": "8",
"speed": "900000",
"switch_id": "1",
"system_port_id": "200"
}
]
}
}
},
"SYSTEM_ASIC_NAME_SUP": {
"sonic-system-port:sonic-system-port": {
"sonic-system-port:SYSTEM_PORT": {
"SYSTEM_PORT_LIST": [
{
"hostname": "host456",
"asic_name": "ASIC12",
"ifname": "Ethernet0",
"core_index": "1",
"core_port_index": "20",
"num_voq": "8",
"speed": "900000",
"switch_id": "1",
"system_port_id": "200"
}
]
}
}
},
"SYSTEM_ASIC_NAME_MIXED_CASE": {
"sonic-system-port:sonic-system-port": {
"sonic-system-port:SYSTEM_PORT": {
"SYSTEM_PORT_LIST": [
{
"hostname": "host456",
"asic_name": "Asic2",
"ifname": "Ethernet0",
"core_index": "1",
"core_port_index": "20",
"num_voq": "8",
"speed": "900000",
"switch_id": "1",
"system_port_id": "200"
}
]
}
}
}

}
4 changes: 1 addition & 3 deletions src/sonic-yang-models/yang-models/sonic-buffer-queue.yang
Original file line number Diff line number Diff line change
Expand Up @@ -84,9 +84,7 @@ module sonic-buffer-queue {
}

leaf asic_name {
type string {
pattern "[Aa]sic[0-4]";
}
type stypes:asic_name;
}

leaf port {
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4 changes: 1 addition & 3 deletions src/sonic-yang-models/yang-models/sonic-queue.yang
Original file line number Diff line number Diff line change
Expand Up @@ -105,9 +105,7 @@ module sonic-queue {
}

leaf asic_name {
type string {
pattern "[Aa]sic[0-4]";
}
type stypes:asic_name;
}

leaf ifname {
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4 changes: 1 addition & 3 deletions src/sonic-yang-models/yang-models/sonic-system-port.yang
Original file line number Diff line number Diff line change
Expand Up @@ -34,9 +34,7 @@ module sonic-system-port {
}

leaf asic_name {
type string {
pattern "[Aa]sic[0-4]";
}
type stypes:asic_name;
}

leaf ifname {
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6 changes: 6 additions & 0 deletions src/sonic-yang-models/yang-templates/sonic-types.yang.j2
Original file line number Diff line number Diff line change
Expand Up @@ -271,6 +271,12 @@ module sonic-types {
}
}

typedef asic_name {
type string {
pattern '[Aa][Ss][Ii][Cc][0-9]{1,2}';
}
}

{% if yang_model_type == "cvl" %}
/* Required for CVL */
container operation {
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