[centec] support v682-48y8c and v682-48x8c #9349
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1. disable wlan config 2. pass iommu=pt for pcie io 3. fix compile error for rtc-sd2405 driver
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This pull request introduces 10 alerts when merging 1822ec7 into 848a171 - view on LGTM.com new alerts:
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Please help to review this PR, Thanks very much, @lguohan @sujinmkang |
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@LuiSzee Do you have command output for v682-48y8c too? And PR description has the v682-48y8c information but it doesn't have v682-48x8c information. Can you also share the output of "docker exec pmon supervisorctl status"? |
Here is the show platform command output on v682-48y8c and v682-48x8c, i also add the output of "docker exec pmon supervisorctl status": V682-48x8c switch has 48 SFP+ (1G/10G) ports, 8 QSFP28 (40G/100G) ports on CENTEC TsingMa.MX, and has similar peripheral device design with V682-48y8c. |
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Please help to review this PR, this PR will upgrade centec sai to v1.9 which will fix the compile problem. |
sujinmkang
added
the
Request for 202111 Branch
Why I did it Adding platform support for centec v682-48y8c and v682-48x8c. V682-48y8c switch has 48 SFP+ (1G/10G/25G) ports, 8 QSFP28 (40G/100G) ports on CENTEC TsingMa.MX. V682-48y8c is different from V682-48y8c_d in that: transceiver is managed by cpu smbus rather than TsingMa.MX i2c bus. port led is managed by mcu inside TsingMa.MX. fan, psu, sensors, leds are managed by cpu smbus other than the cpu board vendor's close sourse driver. V682-48x8c switch has 48 SFP+ (1G/10G) ports, 8 QSFP28 (40G/100G) ports on CENTEC TsingMa.MX. CPU used in v682-48y8c and v682-48x8c is Intel(R) Xeon(R) CPU D-1527. How I did it Modify related code in platform and device directory. Upgrade centec sai to v1.9. upgrade python to python3 and kernel version to 5.0 for V682-48y8c_d. How to verify it Build centec amd64 sonic image, verify platform functions (port, sfp, led etc) on centec v682-48y8c and v682-48x8c board. Co-authored-by: shil <shil@centecnetworks.com>
Why I did it Adding platform support for centec v682-48y8c and v682-48x8c. V682-48y8c switch has 48 SFP+ (1G/10G/25G) ports, 8 QSFP28 (40G/100G) ports on CENTEC TsingMa.MX. V682-48y8c is different from V682-48y8c_d in that: transceiver is managed by cpu smbus rather than TsingMa.MX i2c bus. port led is managed by mcu inside TsingMa.MX. fan, psu, sensors, leds are managed by cpu smbus other than the cpu board vendor's close sourse driver. V682-48x8c switch has 48 SFP+ (1G/10G) ports, 8 QSFP28 (40G/100G) ports on CENTEC TsingMa.MX. CPU used in v682-48y8c and v682-48x8c is Intel(R) Xeon(R) CPU D-1527. How I did it Modify related code in platform and device directory. Upgrade centec sai to v1.9. upgrade python to python3 and kernel version to 5.0 for V682-48y8c_d. How to verify it Build centec amd64 sonic image, verify platform functions (port, sfp, led etc) on centec v682-48y8c and v682-48x8c board. Co-authored-by: shil <shil@centecnetworks.com>
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@sujinmkang - can you add "Request for 202111 branch" label so branch owner can cherrypick? |
Why I did it
Adding platform support for centec v682-48y8c and v682-48x8c.
V682-48y8c switch has 48 SFP+ (1G/10G/25G) ports, 8 QSFP28 (40G/100G) ports on CENTEC TsingMa.MX.
V682-48y8c is different from V682-48y8c_d in that:
V682-48x8c switch has 48 SFP+ (1G/10G) ports, 8 QSFP28 (40G/100G) ports on CENTEC TsingMa.MX.
CPU used in v682-48y8c and v682-48x8c is Intel(R) Xeon(R) CPU D-1527.
How I did it
How to verify it
Build centec amd64 sonic image, verify platform functions (port, sfp, led etc) on centec v682-48y8c and v682-48x8c board.
Which release branch to backport (provide reason below if selected)
undefined reference to sai_query_stats_capabilityon 202111Description for the changelog
A picture of a cute animal (not mandatory but encouraged)