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NPU disable unused PCIe BAR #225

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81 changes: 81 additions & 0 deletions patch/cisco-npu-disable-other-bars.patch
Original file line number Diff line number Diff line change
@@ -0,0 +1,81 @@
From 0be339b4c8468138dfe1a30de29511e94b846af6 Mon Sep 17 00:00:00 2001
From: Madhava Reddy Siddareddygari <msiddare@cisco.com>
Date: Mon, 16 Aug 2021 12:55:37 -0700
Subject: [PATCH] NPU disable unused PCI BAR
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Please make it an upstreamable commit message summary (How to Write a Git Commit Message).


For Cisco ASIC only BAR0 is valid. Not disabling other BAR's
was resulting in pci_enable_device function failure in P0
Pacific ASIC's. Further debugging and consultion with Hardware
team, issue seems to be related to only P0 version of ASIC and
workaround suggested is to disable unused PCI BAR.

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Please also paste the new log messages from one device to the commit message.

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Still open.

Signed-off-by: Madhava Reddy Siddareddygari <msiddare@cisco.com>
---
drivers/pci/quirks.c | 54 ++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 54 insertions(+)

diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
index af2149632..8b99883e1 100644
--- a/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
@@ -5462,3 +5462,57 @@ static void apex_pci_fixup_class(struct pci_dev *pdev)
}
DECLARE_PCI_FIXUP_CLASS_HEADER(0x1ac1, 0x089a,
PCI_CLASS_NOT_DEFINED, 8, apex_pci_fixup_class);
+
+#define PCI_DEVICE_ID_LEABA_PACIFIC 0xabcd
+#define PCI_DEVICE_ID_LEABA_GIBRALTAR 0xa001
+#define PCI_DEVICE_ID_LEABA_GRAPHENE 0xa003
+#define PCI_DEVICE_ID_LEABA_PALLADIUM 0xa004
+#define PCI_DEVICE_ID_LEABA_ARGON 0xa005
+#define PCI_DEVICE_ID_LEABA_KRYPTON 0xa006
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+
+/*
+ * For Pacific A0, only BAR 0 is valid
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Please add an errata document name and number for reference.

+ */
+static void silicon_one_fixup(struct pci_dev *dev)
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I’d think, the function name needs to include cisco somehow.

+{
+ int i;
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This does not follow the Linux coding style. Please check patches with checkpatch.pl script in the Linux kernel.

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Sorry, Firefox display issues in the browser.

+ struct resource *r;
+
+ for (i = 1; i <= PCI_ROM_RESOURCE; i++) {
+ r = &dev->resource[i];
+ if (!r->start && !r->end && !r->flags)
+ continue;
+
+ dev_info(&dev->dev,
+ "Cisco Silicon One BAR %d %pR disabled due to "
+ "NPU hardware bug in P0 Pacific ASIC\n", i, r);
+ r->start = 0;
+ r->end = 0;
+ r->flags = 0;
+ }
+ /*
+ * Pacific device was misbehaving during rescan not enumerating
+ * memory for bar. Due to this HW issue, added this workaround
+ * and verified that during rescan memory gets assigned properly
+ * to the device. This is only a temporary fix for pacific ASIC
Comment on lines +54 to +57
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Maybe:

Due to HW bug, Pacific device is misbehaving during rescan by not enumerating memory for that BAR. Work around it and verify, that during rescan memory gets assigned properly to the device.

+ * only
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Is it really temporary?

+ */
+ dev->class = PCI_CLASS_MEMORY_OTHER << 8;
+ dev_info(&dev->dev, "Cisco Silicon One class adjusted\n");
+}
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SYNOPSYS, PCI_DEVICE_ID_LEABA_PACIFIC,
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Why PCI_VENDOR_ID_SYNOPSYS?

+ silicon_one_fixup);
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CISCO, PCI_DEVICE_ID_LEABA_PACIFIC,
+ silicon_one_fixup);
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CISCO, PCI_DEVICE_ID_LEABA_GIBRALTAR,
+ silicon_one_fixup);
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CISCO, PCI_DEVICE_ID_LEABA_GRAPHENE,
+ silicon_one_fixup);
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CISCO, PCI_DEVICE_ID_LEABA_PALLADIUM,
+ silicon_one_fixup);
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CISCO, PCI_DEVICE_ID_LEABA_ARGON,
+ silicon_one_fixup);
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CISCO, PCI_DEVICE_ID_LEABA_KRYPTON,
+ silicon_one_fixup);
+
+
--
2.26.2

1 change: 1 addition & 0 deletions patch/series
Original file line number Diff line number Diff line change
Expand Up @@ -90,6 +90,7 @@ net-sch_generic-fix-the-missing-new-qdisc-assignment.patch
cisco-mtd-part.patch
cisco-mdio-mux-support-acpi.patch
cisco-x86-gpio-config.patch
cisco-npu-disable-other-bars.patch
#
# Marvell platform patches for 4.19
armhf_secondary_boot_online.patch
Expand Down