Skip to content

Commit

Permalink
[Credo][Ycable] fix incorrect uart statistics (#296)
Browse files Browse the repository at this point in the history
Description
The original get_uart_stat() will only report the last record of the uart statistic due to all record shared the same object instance.

Motivation and Context
How Has This Been Tested?

Signed-off-by: xinyu <xinyu0123@gmail.com>
  • Loading branch information
xinyulin authored and qiluo-msft committed Aug 12, 2022
1 parent ac25515 commit fd8cf3a
Showing 1 changed file with 32 additions and 19 deletions.
51 changes: 32 additions & 19 deletions sonic_y_cable/credo/y_cable_credo.py
Original file line number Diff line number Diff line change
Expand Up @@ -3153,8 +3153,7 @@ def get_uart_stat(self):
"""

if self.platform_chassis is not None:
cnt = {}
uartPort = {}

result = {}

for option in range(2):
Expand All @@ -3166,27 +3165,41 @@ def get_uart_stat(self):
self.log_error('Dump Uart statstics error (error code:0x%04X)' % (status))
return result

addr = 128

for idx in range(1, 3):
cnt['TxPktCnt'] = (self.read_mmap(YCable.MIS_PAGE_FC, addr + 3) << 24) | (self.read_mmap(YCable.MIS_PAGE_FC, addr + 2) << 16) | (self.read_mmap(YCable.MIS_PAGE_FC, addr + 1) << 8) | (self.read_mmap(YCable.MIS_PAGE_FC, addr + 0) << 0)
addr += 4
cnt['RxPktCnt'] = (self.read_mmap(YCable.MIS_PAGE_FC, addr + 3) << 24) | (self.read_mmap(YCable.MIS_PAGE_FC, addr + 2) << 16) | (self.read_mmap(YCable.MIS_PAGE_FC, addr + 1) << 8) | (self.read_mmap(YCable.MIS_PAGE_FC, addr + 0) << 0)
addr += 4
cnt['AckCnt'] = (self.read_mmap(YCable.MIS_PAGE_FC, addr + 3) << 24) | (self.read_mmap(YCable.MIS_PAGE_FC, addr + 2) << 16) | (self.read_mmap(YCable.MIS_PAGE_FC, addr + 1) << 8) | (self.read_mmap(YCable.MIS_PAGE_FC, addr + 0) << 0)
addr += 4
cnt['NackCnt'] = (self.read_mmap(YCable.MIS_PAGE_FC, addr + 3) << 24) | (self.read_mmap(YCable.MIS_PAGE_FC, addr + 2) << 16) | (self.read_mmap(YCable.MIS_PAGE_FC, addr + 1) << 8) | (self.read_mmap(YCable.MIS_PAGE_FC, addr + 0) << 0)
addr += 4
cnt['TxRetryCnt'] = (self.read_mmap(YCable.MIS_PAGE_FC, addr + 3) << 24) | (self.read_mmap(YCable.MIS_PAGE_FC, addr + 2) << 16) | (self.read_mmap(YCable.MIS_PAGE_FC, addr + 1) << 8) | (self.read_mmap(YCable.MIS_PAGE_FC, addr + 0) << 0)
addr += 4
cnt['TxAbortCnt'] = (self.read_mmap(YCable.MIS_PAGE_FC, addr + 3) << 24) | (self.read_mmap(YCable.MIS_PAGE_FC, addr + 2) << 16) | (self.read_mmap(YCable.MIS_PAGE_FC, addr + 1) << 8) | (self.read_mmap(YCable.MIS_PAGE_FC, addr + 0) << 0)
addr += 4
uartPort['UART%d' % idx] = cnt
data = self.read_mmap(YCable.MIS_PAGE_FC, 128, 64)
ver = self.read_mmap(YCable.MIS_PAGE_VSC, 130, 1)

uartPort = {}
cnt = {}
cnt['TxPktCnt'] = struct.unpack_from('<I', data[ 0 : 4])[0]
cnt['RxPktCnt'] = struct.unpack_from('<I', data[ 4 : 8])[0]
cnt['AckCnt'] = struct.unpack_from('<I', data[ 8 : 12])[0]
cnt['NackCnt'] = struct.unpack_from('<I', data[ 12 : 16])[0]
cnt['TxRetryCnt'] = struct.unpack_from('<I', data[ 16 : 20])[0]
cnt['TxAbortCnt'] = struct.unpack_from('<I', data[ 20 : 24])[0]

if ver == 1:
cnt['RxErrorCnt'] = struct.unpack_from('<I', data[ 48 : 52])[0]

uartPort['UART1'] = cnt

cnt = {}
cnt['TxPktCnt'] = struct.unpack_from('<I', data[ 24 : 28])[0]
cnt['RxPktCnt'] = struct.unpack_from('<I', data[ 28 : 32])[0]
cnt['AckCnt'] = struct.unpack_from('<I', data[ 32 : 36])[0]
cnt['NackCnt'] = struct.unpack_from('<I', data[ 36 : 40])[0]
cnt['TxRetryCnt'] = struct.unpack_from('<I', data[ 40 : 44])[0]
cnt['TxAbortCnt'] = struct.unpack_from('<I', data[ 44 : 48])[0]

if ver == 1:
cnt['RxErrorCnt'] = struct.unpack_from('<I', data[ 52 : 56])[0]

uartPort['UART2'] = cnt

if option == 0: result['Local'] = uartPort
else: result['Remote'] = uartPort

else:
self.log_error("platform_chassis is not loaded, failed to get Uart statstics")
self.log_error("platform_chassis is not loaded, failed to get Uart statistics")

return result

Expand Down

0 comments on commit fd8cf3a

Please sign in to comment.